Rose Thompson
73261e7f89
More cleanup. Close to the simpliest it can be.
2024-05-24 16:34:33 -05:00
Rose Thompson
bd2ec879d2
Removed unused axi signals from packetizer.
2024-05-24 16:31:27 -05:00
Rose Thompson
263be86119
Packetizer cleanup.
2024-05-24 16:27:09 -05:00
Rose Thompson
1f7d732dca
Moved the rvvisynth code to testbench since I only want this for simulation and fpga.
2024-05-24 16:10:58 -05:00
Rose Thompson
6e3ccbb9c1
Almost have it working for both buildroot and single elfs.
2024-05-17 17:34:29 -05:00
Rose Thompson
224b2e4dc4
Merge branch 'main' of https://github.com/openhwgroup/cvw
2024-05-17 17:10:28 -05:00
Rose Thompson
038aae388b
Yay. Finally found the issue with the integrated testbench.sv and imperasDV.
...
The function which loads the elf file rvviRefInit must be called during an initial block
using a valid file name. Because of how the testbench was organized the elffile was not defined
until several cycles later so the call to rvviRefInit did not have a valid elf. Waiting several
cycles does not work. rvviRefInit requires being called in an initial block so it is not possible
to run back to back imperasDV simulations in the same run.
2024-05-17 16:45:01 -05:00
Rose Thompson
62eaca0e6e
Almost working ImperasDV with testbench.sv and wally.do. For some reason IDV is saying the instructions are mismatching.
2024-05-16 17:01:25 -05:00
Rose Thompson
8391b8b821
Progress towards unified regression.
2024-05-16 15:29:12 -05:00
Rose Thompson
08601d7270
Added functionallity to testbench.sv for single elf files.
2024-05-16 13:59:15 -05:00
Jordan Carlin
ef778da98d
Eliminate more logical operators and replace with bitwise
2024-05-15 10:50:23 -07:00
Rose Thompson
ceb31fec68
Merge branch 'main' of https://github.com/openhwgroup/cvw
2024-05-10 08:54:23 -05:00
Rose Thompson
b027fa44ef
Merge branch 'main' of https://github.com/openhwgroup/cvw
2024-05-10 08:53:00 -05:00
Rose Thompson
4bd5d334df
Modified testbench so it instantiates the function logger if DEBUG is greater than 0 rather than just 1.
2024-05-10 08:51:59 -05:00
David Harris
66b33c09be
Added Zaamo and Zalrsc support to testbench and regression
2024-05-10 05:41:00 -07:00
David Harris
bdd0043cd1
Testbench terminates buildroot sim at instruction limit
2024-05-09 07:58:53 -07:00
David Harris
47af54b131
Fixed buildroot prematurely terminating in VCS
2024-05-09 07:29:45 -07:00
Divya2030
31ae18922b
regression_wally vcs run works
2024-05-08 04:25:03 -07:00
Divya2030
a3f1a274d2
VCS Simulation Passed
2024-05-07 10:41:02 -07:00
David Harris
06d3591a15
Divy's change for VCS signature checking
2024-05-04 02:45:43 -07:00
Divya2030
ee566aa856
pmp coverage
2024-05-02 11:53:04 -07:00
Divya2030
7a5eac963e
Revert "pmp functional coverage basic"
...
This reverts commit db2b07b05d
2024-05-02 11:43:33 -07:00
Divya2030
9f27f3fe28
Merge branch 'main' of github.com:Divya2030/cvw
2024-05-02 11:21:05 -07:00
Divya2030
db2b07b05d
pmp functional coverage basic
2024-05-02 11:20:03 -07:00
David Harris
e667adf946
Added covergen directed coverage generator
2024-05-01 14:47:37 -07:00
David Harris
6415bfc3c2
Code and testbench cleanup
2024-04-23 10:17:44 -07:00
David Harris
f9eec8c43f
Merged wsim changes
2024-04-22 13:11:35 -07:00
Kunlin Han
9be0303493
Add support for dumping vcd.
2024-04-22 13:03:51 -07:00
David Harris
26711083df
Flushing uart.out file to observe progress
2024-04-21 20:08:35 -07:00
David Harris
03f49dea3f
regression printing improvements
2024-04-21 19:45:09 -07:00
David Harris
be15a11622
Fixed conflicts on getenv
2024-04-21 08:38:13 -07:00
David Harris
00a1c0fc57
Fixed WALLY/RISCV paths in testbench/rom1p1r; search log files for warnings and errors
2024-04-21 00:02:15 -07:00
David Harris
1817ab2e11
testbench import is happy now for Questa, but throws lint warning for VCS
2024-04-20 23:13:13 -07:00
David Harris
fd6a6b2249
environment variable cleanup
2024-04-20 22:52:08 -07:00
David Harris
a1876b1e7c
script cleanup
2024-04-20 17:22:31 -07:00
David Harris
338f37b570
Moved getenv/getenvval declaration to config-shared so lint and regression both run
2024-04-20 17:19:42 -07:00
slmnemo
f0229e970b
Fixed getenvvar verilator bug in rom1p1r, Removed unused system function from testbench.
2024-04-20 17:07:54 -07:00
slmnemo
66a002d879
Removed unused rmCmd string declaration
2024-04-20 16:58:23 -07:00
slmnemo
354d447269
Changed testbench to use fopen instead of opening and closing uartfile whenever writing
2024-04-20 16:56:54 -07:00
Kunlin Han
29c19d9cb4
Add system function through DPI to avoid missing support in Verilator.
2024-04-16 11:23:00 -07:00
Rose Thompson
1eb1beed95
Fixed merge conflict bug in the last pull request.
2024-04-16 10:32:24 -05:00
Rose Thompson
9fe86712d8
Merge branch 'main' into wsim_verilator
2024-04-16 09:07:50 -05:00
David Harris
160162c98a
Merge pull request #728 from Karl-Han/verilator_getenv
...
Add support for getenvval as wrapper for Verilator's getenv
2024-04-15 17:55:34 -06:00
slmnemo
39ae26a897
Added documentation for known Verilator hierarchy bug
2024-04-15 15:58:09 -07:00
slmnemo
4b80457f3e
Fixed issue with Verilator hierarchical referencing by changing module names, moved run-imperas-linux to correct directory
2024-04-12 21:58:20 -07:00
slmnemo
342c99d6ea
Rearranged uart_logger block to only generate if UART is supported
2024-04-12 21:30:33 -07:00
Kunlin Han
eeb5c59143
Remove unnecessary sig and avoid uninitialized signal inside always block.
2024-04-12 16:06:10 -07:00
Kunlin Han
4d9de94029
Add support for getenvval as wrapper for Verilator's getenv.
2024-04-12 14:59:04 -07:00
Rose Thompson
bb072fba84
Fixed the buildroot issue.
2024-04-06 18:25:53 -05:00
Rose Thompson
46fdfde7ec
Removed unnecessary display from testbench.
2024-04-06 16:10:18 -05:00
David Harris
e8111da88a
Removed unused old regression-wally
2024-04-06 13:47:44 -07:00
David Harris
6b844a2e6e
Added GUI support and removed unused wave files
2024-04-06 13:43:06 -07:00
David Harris
3c855e3e90
Passing arguments to buildroot, not yet checking result correctly
2024-04-06 11:42:41 -07:00
David Harris
b3f007ec7f
Working on buildroot in regression
2024-04-06 11:11:22 -07:00
David Harris
ac9a21873d
Pass TEST to testbench with +TEST=<name> rather than -G TEST=<name> so that we don't have to recompile for every new test
2024-04-06 10:34:21 -07:00
slmnemo
d107a42e8c
Replaced rewrite command with system rm command for uart file. Fixed comment on line 573
2024-04-05 21:39:41 -07:00
slmnemo
2fcae601a9
Replaced funky rewrite call with file removal
2024-04-05 20:59:08 -07:00
slmnemo
3ee25c8936
Merged testbench changes
2024-04-05 17:20:03 -07:00
slmnemo
5378b61eb2
Added UART output file buildroot_uart.out for Linux test 'buildroot'.
2024-04-05 17:18:03 -07:00
Divya2030
aa6eacbce5
Merge branch 'openhwgroup:main' into main
2024-04-03 10:40:30 -07:00
Divya2030
135f3b6f8f
vcs testbench
2024-04-03 10:39:02 -07:00
David Harris
8755966f50
Incorporated Kunlin's Verilator hack so testbench runs 110x faster. Isolated within ifdef VERILATOR to make it easier to remove when Verilator issue 4967 is resolved
2024-04-03 07:23:02 -07:00
David Harris
8741b01818
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2024-04-03 06:51:24 -07:00
David Harris
929eb0430c
Testbench uses posedge control signals to speed up Verilator
2024-04-03 06:51:18 -07:00
Rose Thompson
c11d7ea55e
Fixed bug in the testbench which did not allow external memory to work correctly.
2024-04-01 10:59:40 -05:00
David Harris
0caab3c0c9
Removed delays from cacheLRU and testbench
2024-03-25 12:20:25 -07:00
David Harris
b4a914a6e3
Commented out fcvt.h.l tests that don't run on fh_arch64gc arch64zfh; added testbench feature to print when the program jumps to address 0, presumably a bad trap handler
2024-03-14 21:53:30 -07:00
Rose Thompson
3cf6a19729
Merge branch 'main' into main
2024-03-10 10:48:21 -05:00
Rose Thompson
24dffa39d5
Yay. David and I got our first Quad load/store instructions working!
2024-03-07 12:48:52 -06:00
David Harris
b386331cc8
Changed '0 to 0 where possible per Chapter 4 style guidelines
2024-03-06 05:48:17 -08:00
KelvinTr
01c45ab9d7
Fixed K extension changes
2024-02-28 17:05:08 -06:00
Rose Thompson
83dc9cd926
More cleanup.
2024-02-07 15:53:40 -06:00
Rose Thompson
0d008c9281
Merge branch 'main' of https://github.com/openhwgroup/cvw
...
Plus major cleanup of wally-batch.do
2024-02-07 15:44:38 -06:00
Rose Thompson
2acbc95b72
Partially got linux imperas boot working in the main testbench.
2024-02-07 15:38:18 -06:00
Rose Thompson
7f3877f076
Finally have buildroot running in the main testbench!
2024-02-07 11:23:46 -06:00
David Harris
e7364290e3
Restored instead of in testbench because prevents coverage analysis. Improved FPU coverage
2024-02-07 06:27:53 -08:00
Rose Thompson
812c169132
Merge branch 'main' of https://github.com/openhwgroup/cvw
2024-02-06 22:07:09 -06:00
Rose Thompson
5ab88a5daa
Updated to simplify configOptions.
2024-02-06 22:07:06 -06:00
David Harris
d71efedab5
Merge pull request #619 from ross144/main
...
Merged all regression tests except imperas linux boot into testbench.sv.
2024-02-06 16:19:42 -08:00
Rose Thompson
da65928f04
Fixed issue with branch deriv configs.
2024-02-06 16:07:41 -06:00
David Harris
dfee790ad7
Fixed derivative generation when derivs don't already exist. Fixed lint to print success when no failures. Added Zfh fma tests. Some fp tests not running yet.
2024-02-06 12:35:56 -08:00
Rose Thompson
58580445ab
Only output instruction count when the csrs are implemented.
2024-02-05 14:42:27 -06:00
Rose Thompson
8b5970fdc4
Buildroot now reports every 100K instructions as before.
2024-02-05 13:19:48 -06:00
Rose Thompson
c9176f108e
Fixed paths to buildroot objdump label and addr files.
2024-02-05 13:09:31 -06:00
Rose Thompson
17380a68d5
Moved buildroot testbench to the main testbench.
...
However I don't have a positive control or negative indicator to
say when the test completes or passes.
2024-02-05 13:03:48 -06:00
Rose Thompson
44e87f3e3e
First cut at removing the linux testbench and merging build root into the main testbench.
2024-02-05 12:46:14 -06:00
David Harris
66c1c71a56
Coverage improvements
2024-02-04 18:56:40 -08:00
Rose Thompson
d59daf9a6f
Fixed odd bug in the testbench which wasn't skipping signature check for coverage tests.
2024-02-01 12:22:28 -06:00
David Harris
49714cb282
Fixed assertions to throw fatal error, improved nightly regression to have passing cases
2024-01-31 21:39:18 -08:00
David Harris
111f592613
factor divsqrt out of floating-point test cases to run on more derived configs
2024-01-31 14:52:15 -08:00
David Harris
17c9be7695
Cleanup typos, remove Zicond from riscof until it is working
2024-01-18 21:36:52 -08:00
David Harris
0588d611ea
Zfa fli support working for F and D
2024-01-16 17:27:40 -08:00
David Harris
da4eca4854
Tested Zfh support using unreleased version of risch-arch-test Zfh tests. Fixed two bugs in fmv to/from int.
2024-01-15 13:24:57 -08:00
David Harris
9eb6d9c8b8
Added Zicond support
2024-01-11 07:37:15 -08:00
David Harris
d93684be21
Verilate running (slowly)
2024-01-07 21:30:33 -08:00
David Harris
7cd02351d9
Updated testbench to count size of signature without searching for x. Now runs with Verilator.
2024-01-07 09:00:19 -08:00
David Harris
caedab679a
Rewrote testbench to count signature entries rather than looking for x; this will facilitate Verilator which does not use x
2024-01-07 07:14:12 -08:00
David Harris
34f97201ee
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2024-01-06 08:19:56 -08:00
David Harris
167e061a1c
Fixed truncated begin_signature in testbench
2024-01-06 08:19:46 -08:00
Rose Thompson
ab07d64195
Fixes coremark. Maybe works with verilator.
2024-01-06 00:41:57 -06:00
