Ross Thompson
|
9e93f21990
|
Updated covergen to not include stores as they are incomplete.
Modified makefile riscv-dv to not simulation only generate tests.
|
2024-06-19 15:13:49 -07:00 |
|
Jordan Carlin
|
d58b454a8b
|
Finish switching Zfa to use riscv-arch-test
|
2024-06-18 23:31:37 -07:00 |
|
Jordan Carlin
|
6f79dca9c4
|
Merge branch 'main' of https://github.com/openhwgroup/cvw
|
2024-05-27 12:29:24 -07:00 |
|
Quswar Abid
|
997b5901cc
|
sb types are all passing, loaditypes are not!
|
2024-05-27 04:27:50 -07:00 |
|
Quswar Abid
|
1bf9b13953
|
added some sb types
|
2024-05-27 03:58:38 -07:00 |
|
Quswar Abid
|
29d7cd5663
|
unwanted comments
|
2024-05-27 03:58:38 -07:00 |
|
Quswar Abid
|
8edc4057ed
|
compilable tests generating for loaditypes[lb, lh, lw, ld, lbu, lhu, lwu]
|
2024-05-27 03:58:38 -07:00 |
|
Jordan Carlin
|
dcafe4793e
|
Add froundnx and fround.d tests
|
2024-05-24 15:16:35 -07:00 |
|
Jordan Carlin
|
f410bbb79e
|
Use Zfa tests from riscv-arch-test instead of wally-riscv-arch-test
|
2024-05-21 00:04:27 -07:00 |
|
Rose Thompson
|
e295454948
|
Merge pull request #798 from jordancarlin/newConfig
Update config to derive MISA from macros and update MISA bits based on the spec
|
2024-05-15 10:28:44 -05:00 |
|
Jordan Carlin
|
1065b8977a
|
Fix Q_SUPPORTED on derived configs
|
2024-05-14 11:49:54 -07:00 |
|
David Harris
|
990d40410b
|
Test using fpcalc for fp_dataset.py
|
2024-05-14 11:11:24 -07:00 |
|
Shreesh-Kulkarni
|
9aebc1526e
|
Python script to generate coverpoints for the IBM FP Dataset
|
2024-05-14 10:43:32 -07:00 |
|
Shreesh-Kulkarni
|
0887e90367
|
Modified IBM Floating Point Dataset Generator for Quads
|
2024-05-14 10:34:45 -07:00 |
|
David Harris
|
75c10bddfa
|
Moved case.sh to tests/fp
|
2024-05-13 07:12:16 -07:00 |
|
David Harris
|
025e65ce1a
|
Removed unnecessary printing from extract_arch_vectors
|
2024-05-06 06:28:15 -07:00 |
|
David Harris
|
c8269c34a5
|
Changed error to warning
|
2024-05-06 03:50:17 -07:00 |
|
David Harris
|
99282165ae
|
Directed functional coverage tests
|
2024-05-04 02:45:01 -07:00 |
|
David Harris
|
712a167a3a
|
Removed obsolete testgen files
|
2024-05-04 02:44:31 -07:00 |
|
David Harris
|
5d6665cc50
|
More directed testing
|
2024-05-03 11:44:03 -07:00 |
|
David Harris
|
325ec4c8c8
|
Removed obsolete utility
|
2024-05-03 10:58:44 -07:00 |
|
David Harris
|
e667adf946
|
Added covergen directed coverage generator
|
2024-05-01 14:47:37 -07:00 |
|
David Harris
|
b7e66ec7d6
|
Added Zcb tests to riscof
|
2024-04-20 13:17:33 -07:00 |
|
Jordan Carlin
|
6ef6bc042d
|
Update RISCOF ISA config MISA values to be consistent
|
2024-04-06 18:18:50 -07:00 |
|
Rose Thompson
|
b87cdd49a3
|
Merge pull request #690 from davidharrishmc/dev
fcvt.h.l fixes, removed delays
|
2024-03-28 13:42:41 -05:00 |
|
David Harris
|
2b29b107a7
|
Wrote initial covergen for a few R-type instructions
|
2024-03-27 16:22:13 -07:00 |
|
Rose Thompson
|
7c3e93bb2c
|
added lpddrtest.
|
2024-03-26 18:42:48 -05:00 |
|
David Harris
|
4eb7de7381
|
Removed Zfh tests from wally-riscv-arch-test now that they are available in riscv-arch-test
|
2024-03-26 13:58:59 -07:00 |
|
David Harris
|
6688577bc4
|
Fixed fcvt test macro
|
2024-03-25 12:21:15 -07:00 |
|
David Harris
|
690338b758
|
Incorporated fixed fcvt.h.l* instructions; they now run in the testbench
|
2024-03-25 06:08:27 -07:00 |
|
David Harris
|
b3661a0af4
|
Removed unused WALLY-lrsc reference outputs that were incorrect and are not used because Sail is the reference instead
|
2024-03-24 12:31:49 -07:00 |
|
Rose Thompson
|
e97c2cbd83
|
Merge pull request #676 from davidharrishmc/dev
Incorporated Zfa and Zfh tests into wally-riscv-arch-test, mcmodel example code, minor cleanup
|
2024-03-20 09:45:39 -05:00 |
|
Kevin Kim
|
d790a88277
|
fixed bug in intdivrem test vector extraction
|
2024-03-17 14:47:37 -07:00 |
|
David Harris
|
9ff9f9e0ae
|
Updated wally-riscv-arch-test to be able to compile zfh and zfa tests. This caused a change in startup code, so certain reference_output results needed to change to compensate. Also commented out fcvtmod test in Zfa that fails because Sail produces the wrong expected value.
|
2024-03-14 19:03:57 -07:00 |
|
David Harris
|
48799aa87c
|
Added Zfh and Zfa tests to wally-riscv-arch-test until they are accepted in riscv-arch-test repo
|
2024-03-14 10:49:36 -07:00 |
|
David Harris
|
5e3ff3e871
|
Merge pull request #671 from Karl-Han/increase_riscof_jobs
Increase number of jobs in riscof to speedup building.
|
2024-03-13 14:52:05 -07:00 |
|
Kunlin Han
|
b5419ccfc9
|
Increase number of jobs in riscof to speedup building.
|
2024-03-13 12:28:30 -07:00 |
|
Rose Thompson
|
3cf6a19729
|
Merge branch 'main' into main
|
2024-03-10 10:48:21 -05:00 |
|
Rose Thompson
|
402d71e5f4
|
Added basic Quad testing.
|
2024-03-07 15:19:53 -06:00 |
|
Rose Thompson
|
a85ace87c7
|
Sold progress towards a decent q test.
|
2024-03-07 15:01:48 -06:00 |
|
Rose Thompson
|
1872966b0b
|
Progress.
|
2024-03-07 13:02:24 -06:00 |
|
Rose Thompson
|
24dffa39d5
|
Yay. David and I got our first Quad load/store instructions working!
|
2024-03-07 12:48:52 -06:00 |
|
Rose Thompson
|
60f96112db
|
Moved the zero stage boot loader to the fpga directory.
|
2024-03-01 10:23:55 -06:00 |
|
KelvinTr
|
01c45ab9d7
|
Fixed K extension changes
|
2024-02-28 17:05:08 -06:00 |
|
James E. Stine
|
0d4d996655
|
add spike riscof items for K extension test
|
2024-02-24 22:43:33 -06:00 |
|
David Harris
|
824bc0dab7
|
Fixed expected value on WALLY-satp-invalid
|
2024-02-16 11:12:57 -08:00 |
|
Rose Thompson
|
6110799a1e
|
Updated the wally rv32 priv tests to not use sail.
|
2024-02-16 11:39:06 -06:00 |
|
David Harris
|
b362320dd9
|
Removed unused Makefiles and Makefrags from wally-riscv-arch-test now that it is only used by riscof
|
2024-02-16 06:46:49 -08:00 |
|
David Harris
|
d094201362
|
Added NO_SAIL to wally-riscv-arch-test cases that stopped passing in Sail
|
2024-02-16 06:27:49 -08:00 |
|
David Harris
|
9ba35991e3
|
Finished FPU coverage
|
2024-02-15 20:01:28 -08:00 |
|
harshinisrinath
|
86c35bad9f
|
Wrote illegal instructions for remaining floating point instructions
|
2024-02-07 17:13:49 -08:00 |
|
harshinisrinath
|
96c8526754
|
Wrote illegal instructions for remaining floating point instructions
|
2024-02-07 17:08:19 -08:00 |
|
David Harris
|
e7364290e3
|
Restored instead of in testbench because prevents coverage analysis. Improved FPU coverage
|
2024-02-07 06:27:53 -08:00 |
|
David Harris
|
dfee790ad7
|
Fixed derivative generation when derivs don't already exist. Fixed lint to print success when no failures. Added Zfh fma tests. Some fp tests not running yet.
|
2024-02-06 12:35:56 -08:00 |
|
David Harris
|
5d8d82414b
|
Coverage improvements
|
2024-02-04 11:40:38 -08:00 |
|
Jordan Carlin
|
2dce774d34
|
tlb ramline coverage improvements
|
2024-02-03 09:50:15 -08:00 |
|
Jordan Carlin
|
0312476fb3
|
Update tlb camline ASID coverage to use single file
|
2024-02-03 09:48:57 -08:00 |
|
Jordan Carlin
|
8633f263a2
|
Complete coverage of tlb camlines in IFU
|
2024-02-01 20:41:05 -08:00 |
|
Rose Thompson
|
87d91c5b14
|
Coverage updates.
|
2024-02-01 12:12:01 -06:00 |
|
Rose Thompson
|
ccf61853cf
|
New coverage for ebu.
|
2024-01-31 14:55:25 -06:00 |
|
Rose Thompson
|
07d1a4104a
|
Improvement to ebu coverage.
Also modified object dumps to include data segments.
|
2024-01-31 14:03:27 -06:00 |
|
David Harris
|
d9003da8e0
|
Moved some tests to wally-riscv-arch-test list that are simulated
|
2024-01-30 10:28:51 -08:00 |
|
David Harris
|
45e2317636
|
Added Wally github address to header comments
|
2024-01-29 05:38:11 -08:00 |
|
David Harris
|
3620a10c0b
|
Improved hptw and I CacheWays coverage
|
2024-01-26 14:55:51 -08:00 |
|
David Harris
|
1c1d3eb956
|
HPTW coverage improvements
|
2024-01-26 10:46:38 -08:00 |
|
David Harris
|
2449e06e55
|
Fixed FPU coverage, solved Issue 596 by misaligned AMO throwing access fault when misaligned non-amo are supported
|
2024-01-25 21:03:41 -08:00 |
|
David Harris
|
0e1c53f9f6
|
Fixed tlbmisc testing with PBMTE = 0
|
2024-01-24 12:24:33 -08:00 |
|
David Harris
|
66a1edb261
|
More coverage touchup
|
2024-01-23 23:11:49 -08:00 |
|
David Harris
|
7215f48dda
|
coverage improvements: fixing problems running ImperasDV on coverage tests
|
2024-01-23 22:21:01 -08:00 |
|
David Harris
|
d5f497eec5
|
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
|
2024-01-22 09:56:50 -08:00 |
|
Jordan Carlin
|
0c13e14bbf
|
coverage improvements for mret when mpp = 3; update imperas config
|
2024-01-22 09:52:58 -08:00 |
|
David Harris
|
4ffa5e7b0a
|
Coverage improvements
|
2024-01-22 09:49:24 -08:00 |
|
Jordan Carlin
|
4936496bb9
|
fix sfence.inval.ir and sret coverage from previous PR
|
2024-01-22 08:58:31 -08:00 |
|
David Harris
|
171430a695
|
FPU and PMP tests
|
2024-01-21 14:41:22 -08:00 |
|
David Harris
|
ff055c404c
|
fpu coverage improvements
|
2024-01-21 13:17:56 -08:00 |
|
David Harris
|
69218b4b86
|
Coverage improvements
|
2024-01-21 10:03:07 -08:00 |
|
David Harris
|
9260d3c424
|
Add Zfh support to imperas.ic, use Zicond in riscof now that it is fixed in riscv-arch-test
|
2024-01-18 22:46:07 -08:00 |
|
David Harris
|
13de147c7e
|
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
|
2024-01-18 22:12:07 -08:00 |
|
David Harris
|
17c9be7695
|
Cleanup typos, remove Zicond from riscof until it is working
|
2024-01-18 21:36:52 -08:00 |
|
Jordan Carlin
|
82d9467eea
|
Add coverage of FIOM in different privelege modes
|
2024-01-18 19:29:16 -08:00 |
|
Jordan Carlin
|
12b2baff82
|
add coverage of sfence.inval.ir instruction and fix sret coverage
|
2024-01-18 17:33:59 -08:00 |
|
naichewa
|
8b60992e72
|
fixed SPI tests failing when no icache
|
2024-01-17 14:38:11 -08:00 |
|
David Harris
|
f8c88a398a
|
Coverage improvements
|
2024-01-15 07:16:41 -08:00 |
|
Jordan Carlin
|
51f670c821
|
Merge branch 'openhwgroup:main' into main
|
2024-01-12 19:43:01 -08:00 |
|
Jordan Carlin
|
6c797570fa
|
Add coverage for all Zcb instructions
|
2024-01-12 19:10:13 -08:00 |
|
Rose Thompson
|
0b2af0c99a
|
Modifed the sv39 tests so they work with just 128MiB physical memory.
|
2024-01-12 20:00:21 -06:00 |
|
Rose Thompson
|
e6a2595936
|
Modified sv48 svadu test to work with 128MB rather than 2GB physical memory.
|
2024-01-12 11:05:06 -06:00 |
|
David Harris
|
9eb6d9c8b8
|
Added Zicond support
|
2024-01-11 07:37:15 -08:00 |
|
David Harris
|
ba7e017bd9
|
Added Zcb c.lbu coverage test
|
2024-01-10 10:01:46 -08:00 |
|
David Harris
|
d36b6e919a
|
Fixed missing Zba ISA string from spike_rv64gc_isa.yaml for RISCOF
|
2024-01-09 10:00:06 -08:00 |
|
David Harris
|
caedab679a
|
Rewrote testbench to count signature entries rather than looking for x; this will facilitate Verilator which does not use x
|
2024-01-07 07:14:12 -08:00 |
|
David Harris
|
0781cd4a44
|
Improved tlbcontrol to fault on R=0,W=1; fixed more coverage testsin tlbmisc.S; changed integer type to try to speed up CoreMark; comments in Verilate
|
2024-01-05 22:45:15 -08:00 |
|
David Harris
|
ed623f1a71
|
Fixed unsupported riscof YAML string; preparing for Verilator -G testcase
|
2024-01-05 20:06:21 -08:00 |
|
David Harris
|
680a014876
|
Finished LSU tlbcontrol coverage tests
|
2024-01-02 10:16:20 -08:00 |
|
David Harris
|
d229dc06ee
|
Coverage improvements; remove incorrect logic checking NAPOT nonleaf PTE
|
2024-01-02 00:35:17 -08:00 |
|
David Harris
|
52b6d1d163
|
restored tlbNAPOT coverage tests
|
2023-12-31 09:55:58 -08:00 |
|
David Harris
|
b025cd8a0d
|
Updated tlbNAPOT to test instructions as well
|
2023-12-20 23:01:35 -08:00 |
|
David Harris
|
9ced88c55c
|
Fixed tlbNAPOT test to run and makefile to gather coverage stats
|
2023-12-20 21:45:14 -08:00 |
|
David Harris
|
d130a78616
|
Updated to current version of toolchain and prepare to be able to compile Zcb and Zicboz when supported
|
2023-12-20 16:29:03 -08:00 |
|
David Harris
|
0ff049db86
|
Removed unused tests from wally-riscv-arch-test
|
2023-12-20 13:34:12 -08:00 |
|
David Harris
|
8552369687
|
Merged PR538, delete unused tests
|
2023-12-20 13:30:31 -08:00 |
|
Rose Thompson
|
70d0169019
|
All regression tests which matter are running!
|
2023-12-20 14:57:52 -06:00 |
|
Rose Thompson
|
1b59182d59
|
Updated tests with ending label.
|
2023-12-20 14:55:37 -06:00 |
|
Rose Thompson
|
49b1b7c7f9
|
Fixed the last uninitialized memory issue in the priv tests.
|
2023-12-19 16:51:56 -06:00 |
|
Rose Thompson
|
b04ad23c33
|
Fixed bugs in the wally64periph signature.
|
2023-12-19 16:16:59 -06:00 |
|
Rose Thompson
|
726efee1e2
|
Fixed bugs in the cbom test.
|
2023-12-19 15:53:48 -06:00 |
|
Rose Thompson
|
418ae0decc
|
Fixed some regression tests with David's help.
|
2023-12-19 14:18:21 -06:00 |
|
David Harris
|
a138ef37b1
|
Switched to using riscv-arch-test rv32e_m suite. Need to rename it from rv32e_unratified (PR pending)
|
2023-12-15 19:26:50 -08:00 |
|
David Harris
|
38f4d9baf8
|
Use riscv-arch-test arch32e instead of outdated wally-riscv-arch-test wally32e
|
2023-12-15 05:05:53 -08:00 |
|
David Harris
|
29f57958a9
|
Fixed WALLY-lrsc in ImperasDV by setting reservation set size to native word size and adjusting imperas.ic lr_sc_grain=8 to match
|
2023-12-14 15:32:36 -08:00 |
|
David Harris
|
166c98b6f6
|
Fixed issue 526 about WALLY-mmu-sv39-svadu-svnapot-svpbmt not checking ppn for NAPOT pages. Improved test case to check normal and malformed ppn
|
2023-12-13 19:43:17 -08:00 |
|
David Harris
|
6c017141c5
|
Renamed HADE to ADUE for Svadu
|
2023-12-13 11:49:04 -08:00 |
|
David Harris
|
0f0b4b0c1c
|
Added make wally-riscv-arch-test to tests/riscof to only build custom tests
|
2023-12-06 07:19:12 -08:00 |
|
David Harris
|
2b2016271a
|
repo cleanup and start to add CMO tests
|
2023-11-20 23:41:36 -08:00 |
|
Rose Thompson
|
540d8d930d
|
Cleanup.
Linux makefile
wally tracer. probably reduce some complexity here.
|
2023-11-13 14:04:43 -06:00 |
|
Rose Thompson
|
9dfe421c55
|
Yay! Zicclsm passes my regression test now.
|
2023-11-10 18:28:51 -06:00 |
|
Rose Thompson
|
c0e02ae190
|
Found another bug in the RTL's Zicclsm alignment.
|
2023-11-10 18:26:55 -06:00 |
|
Rose Thompson
|
02ab9fe99c
|
Fixed all the bugs associated with the signature and the store side of misaligned access. Load misaligned is still causing some issues.
|
2023-11-10 17:58:42 -06:00 |
|
Rose Thompson
|
bd866e1025
|
Fixed some more bugs in the Zicclsm signature.
|
2023-11-10 17:36:10 -06:00 |
|
Rose Thompson
|
efecb0c346
|
Fixed bug in the Zicclsm test.
|
2023-11-10 17:34:23 -06:00 |
|
Rose Thompson
|
ada354f443
|
Fixed bug in the misaligned access test.
|
2023-11-10 17:02:15 -06:00 |
|
Rose Thompson
|
b74bfbeefd
|
Merge branch 'main' into Zicclsm
|
2023-11-10 16:15:32 -06:00 |
|
naichewa
|
d67badfc60
|
fix hardware interlock, hold mode deassert
|
2023-11-08 15:20:51 -08:00 |
|
naichewa
|
a5837eb62c
|
fifo fixes and edge case testing
|
2023-11-07 17:59:46 -08:00 |
|
naichewa
|
4651b807ed
|
added test cases
|
2023-11-02 15:43:08 -07:00 |
|
Rose Thompson
|
0a4ed5515b
|
Merge branch 'main' into Zicclsm
|
2023-11-02 12:55:51 -05:00 |
|
Rose Thompson
|
afa1d85e3b
|
Doesn't yet fully work.
Thomas is going to finish debugging while I'm on the RISCV summit next week.
|
2023-11-02 12:07:42 -05:00 |
|
Rose Thompson
|
7ba891f607
|
Progress. I think the remaining bugs are in the regression test's signature.
|
2023-11-01 17:51:48 -05:00 |
|
naichewa
|
9aa8a7af3e
|
comments, more test cases
|
2023-11-01 01:26:34 -07:00 |
|
Rose Thompson
|
5660eff57d
|
Working through issues with the psill logic.
|
2023-10-31 18:50:13 -05:00 |
|
Rose Thompson
|
4984b3935f
|
Progress
|
2023-10-31 14:50:33 -05:00 |
|
Rose Thompson
|
5ca428d6a8
|
Fixed bugs in misaligned test.
|
2023-10-31 12:49:35 -05:00 |
|
Rose Thompson
|
c061440141
|
First stab at the misaligned test.
|
2023-10-31 12:30:10 -05:00 |
|
naichewa
|
7dd3f24d6c
|
Merge branch 'main' into spi
|
2023-10-30 17:01:41 -07:00 |
|
naichewa
|
2330f4ee63
|
hardware interlock
|
2023-10-30 17:00:20 -07:00 |
|
Rose Thompson
|
2241976d29
|
Updated mmu to not generate trap on cacheable misaligned access when supported.
Updated tests with David's help.
|
2023-10-30 18:26:11 -05:00 |
|
David Harris
|
f6a7f707bd
|
Fixed test cases for medeleg issue 444. Also added a COMPRESSED_SUPPORTED parameter true when C or Zca is supported, and use this to get compressed hardware such as the spill logic and the +2 adder.
|
2023-10-30 09:56:17 -07:00 |
|
Rose Thompson
|
0fd5b3b2ce
|
Updated comments in the cboz tests.
|
2023-10-20 15:15:47 -05:00 |
|
Rose Thompson
|
5a4028064a
|
Updated comments for the cbom tests.
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2023-10-20 15:13:52 -05:00 |
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naichewa
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0ff9ce527d
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Merge branch 'main' into spi
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2023-10-16 22:59:50 -07:00 |
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David Harris
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ac4216b43d
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Incorporated new AMO tests from riscv-arch-test
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2023-10-16 10:25:45 -07:00 |
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David Harris
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6245748ed7
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Added CSR permission tests for mconfigptr, menvcfg, mseccfg, etc.
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2023-10-15 15:31:03 -07:00 |
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David Harris
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b4891d88db
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Added WALLY minfo test for rv32
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2023-10-15 06:48:22 -07:00 |
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David Harris
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434d6b2c5c
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minfo test working again with mconfigptr for RV64
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2023-10-15 06:41:52 -07:00 |
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naichewa
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aa5abfc8e8
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always working after reg bit swizzle changes
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2023-10-13 14:22:32 -07:00 |
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naichewa
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f231c3d3a3
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correct delay0, fmt register test entries
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2023-10-12 15:13:23 -07:00 |
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naichewa
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d5d4f9d044
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transferred spi changes in ECA-authorized commit
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2023-10-12 13:36:57 -07:00 |
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David Harris
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d526d28804
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Added MENVCFG.HADE bit and updated SVADU to depend on this bit
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2023-10-04 09:34:28 -07:00 |
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Ross Thompson
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9ff3642c6c
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Merge branch 'main' of https://github.com/openhwgroup/cvw
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2023-09-05 11:12:00 -05:00 |
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David Harris
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9747d122d2
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tlbNAPOT hangs due to PBMT making instruction memory uncacheable, and spill logic not working there. Fixed TLBLRU to update recently used on TLBHit rather than CAMHit. Moved coverage exclusions to proper line in pmachecker
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2023-09-02 12:56:36 -07:00 |
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