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389 Commits

Author SHA1 Message Date
Ross Thompson
0bfbcef8ab Now past the CLINT issues. 2021-08-06 16:16:39 -05:00
Ross Thompson
9be10cdc8b Partial conversion of the linux trace checking to read in the file in the Memory Stage so it is possible to overwrite registers, memory, and interrupts. 2021-08-06 16:06:50 -05:00
Ross Thompson
c749d08542 fixed the read timer issue but we still have problems with interrupts and i/o devices. 2021-08-06 10:16:06 -05:00
Ross Thompson
e166cc84ee Patched up changes for wally-pipelined.do and wally-buildroot.do to support moved common testbench files. 2021-07-30 14:24:50 -05:00
Ross Thompson
74fba4bb06 Moved the test bench modules to a common directory. 2021-07-30 14:16:14 -05:00
Ross Thompson
3e916da36e Removed the hardware page table walker fault state from the icache so that the icache will only unstall CPU for 1 cycle. 
In the dcache we added a register to save the load read data in the event an itlb miss occurs concurrently with
the load in the memory stage.  Under this situation we need to record the load ReadDataM into a temporary register,
SavedReadDataM.  At this time the CPU is stall; however the walker is going to change the address in the dcache
which destroys this data.  When leaving the PTW_READY state via a walker instruction fault or ITLB write we select
this SavedReadDataM so that the CPU can capture it.
 2021-07-22 19:42:19 -05:00
Ross Thompson
551e3491af Moved the ReadDataW register into the datapath. 
The StallW from the hazard unit controls this.
Previously it was in the dcache and controlled by both the HPTW and hazard unit.
This caused an issue when the CPU expected the data to stay constant while
stalled, but the HPTW was causing the data to be modified.
 2021-07-22 14:52:03 -05:00
Ross Thompson
3dd89a7e62 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-22 10:38:24 -05:00
Ross Thompson
25a8920a69 Tested all numbers of ways for dcache 1, 2, 4, and 8. 2021-07-22 10:38:07 -05:00
bbracker
d3059dd04c fix UART RX FIFO bug where tail pointer can overtake head pointer 2021-07-22 02:09:41 -04:00
bbracker
57a2917997 make address translator signals visible in waveview 2021-07-21 20:07:49 -04:00
Ross Thompson
313bc5255c Improved address bus names and usages in the walker, dcache, and tlbs. 
Merge branch 'walkerEnhance' into main
 2021-07-21 14:55:09 -05:00
Ross Thompson
e0990535e1 Fixed remaining bugs in 2 way set associative dcache. 2021-07-21 10:35:23 -05:00
Ross Thompson
14e949d6e3 Partially working 2 way set associative d cache. 2021-07-20 17:51:42 -05:00
bbracker
1aeef4e7d1 remove busybear from regression because it is not keeping up with buildroot's changes to testbench-linux 2021-07-19 16:22:05 -04:00
bbracker
cd469035be make testbench check the same CSRs that QEMU logs; change CLINT to reset MTIMECMP to -1 so that we don't instantly get a timer interrupt upon reset 2021-07-19 15:13:03 -04:00
Ross Thompson
9f76e1d64d Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-19 12:32:35 -05:00
Ross Thompson
b61dad4b83 Fixed a complex bug in the dcache, where back to back loads would lose data on the load before a stall occurred. The solution was to modify the logic for SelAdrM in the dcache so that a stall would cause the SRAM to reread the address in the Memory stage rather than Execution stage. This also required updating the ReadDataWEn control so it is always enabled on ~StallW. 2021-07-19 12:32:16 -05:00
bbracker
f31a0ded75 change buildroot expectations to match reality 2021-07-19 13:20:53 -04:00
Ross Thompson
4d53b9002f Broken. 
Possible change to walker, dcache, tlb addressing.
Improves the naming of address signals.
But has a problem when the walker finishes the dcache does not get the correct
address on the cycle the DTLB is updated.  This leads to incorrect index
selection in the dcache.
 2021-07-19 10:33:27 -05:00
bbracker
e4a50a5bb8 change memread testvectors to not left-shift bytes and half-words 2021-07-18 21:49:53 -04:00
bbracker
5e9dcb3f1c linux testbench progress 2021-07-18 18:47:40 -04:00
Katherine Parry
60dabb9094 fdivsqrt inegrated, but not completley working 2021-07-18 14:03:37 -04:00
bbracker
18fb282a37 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-17 14:46:38 -04:00
bbracker
4a3503281f swapped out linux testbench signal names 2021-07-17 14:46:18 -04:00
David Harris
87aa527de7 hptw: minor cleanup 2021-07-17 13:40:12 -04:00
Ross Thompson
6521d2b468 Also changed the shadow ram's dcache copy widths. 
Merge branch 'dcache' into main
 2021-07-16 14:21:09 -05:00
Ross Thompson
b3bf04d474 Updated wave file. 2021-07-16 12:34:37 -05:00
Ross Thompson
46bce70e42 Fixed walker fault interaction with dcache. 2021-07-16 12:22:13 -05:00
bbracker
01ca22af49 changed stop of linux boot from arch_cpu_idle to do_idle 2021-07-16 12:27:15 -04:00
Ross Thompson
e5d624c1fa Found bug in the PMA such that invalid addresses were sent to the tim. Once addressing this issue the sv48 test fails early with a pma access fault. 2021-07-15 11:56:35 -05:00
Ross Thompson
fa26aec588 Merge branch 'main' into dcache 2021-07-15 11:55:20 -05:00
Ross Thompson
fd1de6b047 Updated wave file. 2021-07-15 11:04:49 -05:00
Ross Thompson
704f4f724e dcache STATE_CPU_BUSY needs to assert CommittedM. This is required to ensure a completed memory operation is not bound to an interrupt. ie. MEPC should not be PCM when committed. 2021-07-14 23:08:07 -05:00
Ross Thompson
ba1e1ec231 Finally have the ptw correctly walking through the dcache to update the itlb. 
Still not working fully.
 2021-07-14 22:26:07 -05:00
Katherine Parry
c74d26eea4 Fixed lint warning 2021-07-14 21:24:48 -04:00
Ross Thompson
2c946a282f Fixed d cache not honoring StallW for uncache writes and reads. 2021-07-14 17:23:28 -05:00
Ross Thompson
e91501985c Routed CommittedM and PendingInterruptM through the lsu arb. 2021-07-14 16:18:09 -05:00
Ross Thompson
9b756d6a94 Implemented uncached reads. 2021-07-13 23:03:09 -05:00
Ross Thompson
3e57c899a2 Partially working changes to support uncached memory access. Not sure what CommitedM is. 2021-07-13 17:24:59 -05:00
Ross Thompson
baa2b5d15f Fixed interaction between icache stall and dcache. On hit dcache needs to enter a cpu busy state when the cpu is stalled. 2021-07-13 14:51:42 -05:00
Ross Thompson
3c1a717399 Fixed the fetch buffer accidental overwrite on eviction. 2021-07-13 14:21:29 -05:00
Ross Thompson
32f27cfecf Dcache AHB address generation was wrong. Needed to zero the offset. 2021-07-13 14:19:04 -05:00
Ross Thompson
afc1bc9c38 Moved StoreStall into the hazard unit instead of in the d cache. 2021-07-13 13:20:50 -05:00
David Harris
9de97c1e20 Fixed busybear by restoring InstrValidW needed by testbench 2021-07-13 14:17:36 -04:00
Katherine Parry
efdec72df1 Fixed writting MStatus FS bits 2021-07-13 13:20:30 -04:00
Ross Thompson
e594eb540d Got the shadow ram cache flush working. 2021-07-13 10:03:47 -05:00
Ross Thompson
49f6eec579 Team work on solving the dcache data inconsistency problem. 2021-07-12 23:46:32 -05:00
Ross Thompson
1cc258ade1 Progress towards the test bench flush. 2021-07-12 14:22:13 -05:00
Katherine Parry
36f59f3c99 Almost all convert instructions pass Imperas tests 2021-07-11 18:06:33 -04:00
Ross Thompson
60ed023734 Actually writes the correct data now on stores. 2021-07-10 17:48:47 -05:00
Ross Thompson
6e7e318396 Fixed bug in the LSU pagetable walker interlock. 2021-07-06 10:41:36 -05:00
Ross Thompson
2a62ee2e70 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-05 16:07:27 -05:00
David Harris
5f91b339aa Added F_SUPPORTED flag to disable floating point unit when not in MISA 2021-07-05 10:30:46 -04:00
Ross Thompson
a252416535 Removed the TranslationVAdrQ as it is not necessary. 2021-07-04 16:49:34 -05:00
Ross Thompson
7f62808544 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-04 16:19:39 -05:00
Ross Thompson
5b70eb86b0 relocated lsuarb and pagetable walker inside the lsu. Does not pass busybear or buildroot, but passes rv32ic and rv64ic. 2021-07-04 13:49:38 -05:00
David Harris
9645b023c9 Moved BOOTTIM to 0x1000-0x1FFF. Added logic to detect an access to undefined memory and assert HREADY so bus doesn't hang. 2021-07-04 01:19:38 -04:00
Ben Bracker
59b177beac stop busybear from hanging 2021-07-02 17:22:09 -05:00
Ross Thompson
dbd33465e1 Merge branch 'main' into bigbadbranch 2021-07-02 11:52:26 -05:00
Ross Thompson
61027f650c OMG. It's working! 2021-07-01 17:37:53 -05:00
Ross Thompson
2dc349ea6f Fixed the wrong virtual address write into the dtlb. 2021-07-01 16:55:16 -05:00
Ross Thompson
88a18496cf Got some stores working in virtual memory. 2021-07-01 12:49:09 -05:00
Ross Thompson
002c32d2ad The icache ptw interlock is actually correct now. There needed to be a 1 cycle delay. 2021-06-30 17:02:36 -05:00
Ross Thompson
9ec624702d Major rewrite of ptw to remove combo loop. 2021-06-30 16:25:03 -05:00
Ross Thompson
b2d8ba6742 The icache now correctly interlocks with the PTW on TLB miss. 2021-06-30 11:24:26 -05:00
Ross Thompson
dd84f2958e Page table walker now walks the table. 
Added interlock so the icache stalls.
Page table walker not walking correctly, goes to fault state.
 2021-06-29 22:33:57 -05:00
Ross Thompson
bc9c944ba0 Don't use this branch walker still broken. 2021-06-28 17:26:11 -05:00
Ross Thompson
d80ebab941 AMO and LR/SC instructions now working correctly. 
Page table walking is not working.
 2021-06-25 15:42:07 -05:00
Ross Thompson
b4a788c341 Working through a combo loop. 2021-06-25 14:49:27 -05:00
Ross Thompson
d6c19e73f4 Regression test runs further. The LSU state machine which fakes the Dcache had a few bugs. MemAccessM needed to be squashed on bus faults. 2021-06-25 11:05:17 -05:00
bbracker
13cf7c0934 linux testbench now ignores HWRITE glitches caused by flush glitches 2021-06-25 09:28:52 -04:00
Ross Thompson
6bab454b17 Works until pma checker breaks the simulation by reading HADDR rather than data physical address. 2021-06-24 14:42:59 -05:00
bbracker
53d545cdfe regression can overcome the fact that buildroots UART prints stuff 2021-06-24 02:00:01 -04:00
bbracker
cee468b21a whoops meant to remove notifications from busybear, not buildroot 2021-06-24 01:54:46 -04:00
bbracker
be962cb1ff overhauled linux testbench and spoofed MTTIME interrupt 2021-06-24 01:42:35 -04:00
David Harris
a514554eeb Reduced complexity of pmpadrdec 2021-06-23 03:03:52 -04:00
bbracker
9b27cd6fb7 added slack notifier for long sims 2021-06-22 08:31:41 -04:00
bbracker
2643130c41 read from MSTATUS workaround because QEMU has incorrect MSTATUS 2021-06-20 10:11:39 -04:00
bbracker
dc26f2a6d0 whoops wavedo typo 2021-06-20 05:36:54 -04:00
bbracker
c77aabdc6f make buildroot ignore SSTATUS because QEMU did not originally log it 2021-06-20 05:31:24 -04:00
bbracker
086f031b84 remove lingering busybear stuff from buildroot do files 2021-06-20 00:50:53 -04:00
bbracker
d62d9a7aac make buildroot waves only turn on after a user-specified point 2021-06-20 00:39:30 -04:00
David Harris
33312caeb1 Restored wally-busybear testbench now that graphical sim is working 2021-06-18 12:36:25 -04:00
bbracker
4f50dd575d buildroot added to regression because it passes regression 2021-06-18 09:49:30 -04:00
David Harris
336936cc39 Cleaned up name of MTIME register in CSRC 2021-06-18 07:53:49 -04:00
bbracker
5b96f7fbd7 making linux waveforms more useful 2021-06-17 08:37:37 -04:00
bbracker
28c6d60150 temporarily removing buildroot from regression until it is regenerated 2021-06-07 13:20:50 -04:00
David Harris
dc0b19dfaa Merge difficulties 2021-06-07 09:50:23 -04:00
David Harris
d5ec797ba4 Refactored configuration files and renamed testbench-busybear to testbench-linux 2021-06-07 09:46:52 -04:00
Ross Thompson
41a1e6112a Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-06-04 15:16:39 -05:00
Ross Thompson
7406e33b61 Continued I-Cache cleanup. 
Removed strange mux on InstrRawD along with
the select logic.
 2021-06-04 15:14:05 -05:00
Ross Thompson
191f7e61fd Moved I-Cache offset selection mux to icache.sv (top level). 
When we switch to set associative this is will be more efficient.
 2021-06-04 13:49:33 -05:00
Katherine Parry
fc65aedbd6 Double-precision FMA instructions 2021-06-04 14:00:11 -04:00
Ross Thompson
fdef8df76b Reorganized the icache names. 2021-06-04 12:53:42 -05:00
David Harris
0674f5506e moved shared constants to a shared directory 2021-06-03 22:41:30 -04:00
bbracker
4e765ee1c5 expanded GPIO testing and caught small GPIO bug 2021-06-03 10:03:09 -04:00
bbracker
2c77a13c08 fixed InstrValid signals and implemented less costly MEPC loading 2021-06-02 10:03:19 -04:00
bbracker
39ae743543 turns out I should not have tried renaming FStallD to FPUStallD because that name was already used! All the same it does feel weird to have two such signals floating around \(ah pun!\) 2021-05-28 23:11:37 -04:00
bbracker
846553ac7d improved PLIC test organization 2021-05-21 15:13:02 -04:00