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make testbench check the same CSRs that QEMU logs; change CLINT to reset MTIMECMP to -1 so that we don't instantly get a timer interrupt upon reset

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This commit is contained in:
bbracker 2021-07-19 15:13:03 -04:00
parent 9f76e1d64d
commit cd469035be
4 changed files with 47 additions and 36 deletions
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13
wally-pipelined/regression/wave-dos/linux-waves.do
View File

@ -282,12 +282,13 @@ add wave -noupdate -radix hexadecimal /testbench/PCW
add wave -noupdate -radix hexadecimal /testbench/PCtextW
add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/InstrValidW
add wave -noupdate /testbench/dut/hart/ieu/dp/ReadDataW
add wave -noupdate /testbench/dut/hart/ieu/dp/RegWriteW
add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/ResultW
add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/RdW
add wave -noupdate -divider RegFile
add wave -noupdate /testbench/dut/hart/ieu/dp/RegWriteW
add wave -noupdate -radix unsigned /testbench/regNumExpected
add wave -noupdate -radix unsigned /testbench/dut/hart/ieu/dp/RdW
add wave -noupdate -radix hexadecimal /testbench/regExpected
add wave -noupdate -radix hexadecimal /testbench/regNumExpected
add wave -noupdate /testbench/dut/hart/ieu/dp/regf/wd3
add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[2]}
add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[3]}
add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[4]}
@ -25536,8 +25537,8 @@ add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HADDR
add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HWRITE
add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HWDATA
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 8} {2495 ns} 1} {{Cursor 2} {210 ns} 0}
quietly wave cursor active 2
WaveRestoreCursors {{Cursor 8} {203758 ns} 0} {{Cursor 2} {203765 ns} 1}
quietly wave cursor active 1
configure wave -namecolwidth 250
configure wave -valuecolwidth 297
configure wave -justifyvalue left
@ -25552,4 +25553,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {2395 ns} {2605 ns}
WaveRestoreZoom {203642 ns} {203852 ns}

7
wally-pipelined/src/privileged/csrm.sv
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@ -82,7 +82,7 @@ module csrm #(parameter
output logic IllegalCSRMAccessM, IllegalCSRMWriteReadonlyM
);
logic [`XLEN-1:0] MISA_REGW;
logic [`XLEN-1:0] MISA_REGW, MHARTID_REGW;
logic [`XLEN-1:0] MSCRATCH_REGW, MCAUSE_REGW, MTVAL_REGW;
logic WriteMTVECM, WriteMEDELEGM, WriteMIDELEGM;
@ -97,6 +97,9 @@ module csrm #(parameter
// MISA is hardwired. Spec says it could be written to disable features, but this is not supported by Wally
assign MISA_REGW = {(`XLEN == 32 ? 2'b01 : 2'b10), {(`XLEN-28){1'b0}}, MISA_26[25:0]};
// MHARTID is hardwired. It only exists as a signal so that the testbench can easily see it.
assign MHARTID_REGW = 0;
// Write machine Mode CSRs
assign WriteMSTATUSM = CSRMWriteM && (CSRAdrM == MSTATUS) && ~StallW;
assign WriteMTVECM = CSRMWriteM && (CSRAdrM == MTVEC) && ~StallW;
@ -195,7 +198,7 @@ module csrm #(parameter
MVENDORID: CSRMReadValM = 0;
MARCHID: CSRMReadValM = 0;
MIMPID: CSRMReadValM = `XLEN'h100; // pipelined implementation
MHARTID: CSRMReadValM = 0;
MHARTID: CSRMReadValM = MHARTID_REGW; // hardwired to 0
MSTATUS: CSRMReadValM = MSTATUS_REGW;
MSTATUSH: CSRMReadValM = 0; // flush this out later if MBE and SBE fields are supported
MTVEC: CSRMReadValM = MTVEC_REGW;

4
wally-pipelined/src/uncore/clint.sv
View File

@ -82,7 +82,7 @@ module clint (
always_ff @(posedge HCLK or negedge HRESETn)
if (~HRESETn) begin
MSIP <= 0;
MTIMECMP <= 0;
MTIMECMP <= (`XLEN)'(-1);
// MTIMECMP is not reset
end else if (memwrite) begin
if (entryd == 16'h0000) MSIP <= HWDATA[0];
@ -112,7 +112,7 @@ module clint (
always_ff @(posedge HCLK or negedge HRESETn)
if (~HRESETn) begin
MSIP <= 0;
MTIMECMP <= 0;
MTIMECMP <= (`XLEN)'(-1);
// MTIMECMP is not reset
end else if (memwrite) begin
if (entryd == 16'h0000) MSIP <= HWDATA[0];

59
wally-pipelined/testbench/testbench-linux.sv
View File

@ -27,7 +27,7 @@
module testbench();
parameter waveOnICount = `BUSYBEAR*140000 + `BUILDROOT*0000000; // # of instructions at which to turn on waves in graphical sim
parameter waveOnICount = `BUSYBEAR*140000 + `BUILDROOT*0459700; // # of instructions at which to turn on waves in graphical sim
parameter stopICount = `BUSYBEAR*143898 + `BUILDROOT*0000000; // # instructions at which to halt sim completely (set to 0 to let it run as far as it can)
///////////////////////////////////////////////////////////////////////////////
@ -530,7 +530,7 @@ module testbench();
// --------------
// Checker Macros
// --------------
string MSTATUSstring = "MSTATUS"; //string variables seem to compare more reliably than string literals
string MSTATUSstring = "MSTATUS"; // string variables seem to compare more reliably than string literals (they gave me a lot of hassle), but *** there's probably a better way to do this
string SEPCstring = "SEPC";
string SCAUSEstring = "SCAUSE";
string SSTATUSstring = "SSTATUS";
@ -541,9 +541,11 @@ module testbench();
string expected``CSR``name; \
always @(``PATH``.``CSR``_REGW) begin \
if ($time > 1 && (`BUILDROOT != 1 || ``CSR``name != SSTATUSstring)) begin \
if (``CSR``name == SEPCstring) begin #1; end \
if (``CSR``name == SCAUSEstring) begin #2; end \
if (``CSR``name == SSTATUSstring) begin #3; end \
// This is some feeble hackery designed to control the order in which CSRs are checked \
// when multiple change at the same time. \
if (``CSR``name == SEPCstring) #1; \
if (``CSR``name == SCAUSEstring) #2; \
if (``CSR``name == SSTATUSstring) #3; \
scan_file_csr = $fscanf(data_file_csr, "%s\n", expected``CSR``name); \
scan_file_csr = $fscanf(data_file_csr, "%x\n", expected``CSR``); \
if(expected``CSR``name.icompare(``CSR``name)) begin \
@ -581,31 +583,36 @@ module testbench();
// --------
// Checking
// --------
//`CHECK_CSR(FCSR)
`CHECK_CSR2(MCAUSE, `CSRM)
`CHECK_CSR(MCOUNTEREN)
`CHECK_CSR(MEDELEG)
`CHECK_CSR(MEPC)
//`CHECK_CSR(MHARTID)
`CHECK_CSR(MIDELEG)
`CHECK_CSR(MIE)
//`CHECK_CSR(MIP)
`CHECK_CSR2(MISA, `CSRM)
`CHECK_CSR2(MSCRATCH, `CSRM)
// Which CSRs we check depends upon which ones QEMU outputs
// *** can we fix QEMU to output a defined set of CSRs?
`CHECK_CSR2(MHARTID, `CSRM)
`CHECK_CSR(MSTATUS)
`CHECK_CSR2(MTVAL, `CSRM)
`CHECK_CSR(MIP)
`CHECK_CSR(MIE)
`CHECK_CSR(MIDELEG)
`CHECK_CSR(MEDELEG)
`CHECK_CSR(MTVEC)
`CHECK_CSR(STVEC)
`CHECK_CSR(MEPC)
`CHECK_CSR(SEPC)
`CHECK_CSR2(MCAUSE, `CSRM)
`CHECK_CSR2(SCAUSE, `CSRS)
`CHECK_CSR2(MTVAL, `CSRM)
`CHECK_CSR2(STVAL, `CSRS)
//`CHECK_CSR(FCSR)
//`CHECK_CSR(MCOUNTEREN)
//`CHECK_CSR2(MISA, `CSRM)
//`CHECK_CSR2(MSCRATCH, `CSRM)
//`CHECK_CSR2(PMPADDR0, `CSRM)
//`CHECK_CSR2(PMdut.PCFG0, `CSRM)
`CHECK_CSR(SATP)
`CHECK_CSR2(SCAUSE, `CSRS)
`CHECK_CSR(SCOUNTEREN)
`CHECK_CSR(SEPC)
`CHECK_CSR(SIE)
`CHECK_CSR2(SSCRATCH, `CSRS)
`CHECK_CSR(SSTATUS)
`CHECK_CSR2(STVAL, `CSRS)
`CHECK_CSR(STVEC)
//`CHECK_CSR(SATP)
//`CHECK_CSR(SCOUNTEREN)
//`CHECK_CSR(SIE)
//`CHECK_CSR2(SSCRATCH, `CSRS)
//`CHECK_CSR(SSTATUS)
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////// Miscellaneous ///////////////////////////////