forked from Github_Repos/cvw
Tested all numbers of ways for dcache 1, 2, 4, and 8.
This commit is contained in:
Ross Thompson
parent
dac93bb366
commit
25a8920a69
@ -255,10 +255,12 @@ add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/DCacheMemWriteData
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group replacement /testbench/dut/hart/lsu/dcache/genblk2/cacheLRU/LRUIn
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group replacement /testbench/dut/hart/lsu/dcache/genblk2/cacheLRU/WayIn
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group replacement /testbench/dut/hart/lsu/dcache/genblk2/cacheLRU/NewLRUEn
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group replacement /testbench/dut/hart/lsu/dcache/genblk2/cacheLRU/LRUEn
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group replacement /testbench/dut/hart/lsu/dcache/genblk2/cacheLRU/LRUMask
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group replacement /testbench/dut/hart/lsu/dcache/genblk2/cacheLRU/LRUOut
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group replacement /testbench/dut/hart/lsu/dcache/genblk2/cacheLRU/VictimWay
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} /testbench/dut/hart/lsu/dcache/ReplacementBits
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} /testbench/dut/hart/lsu/dcache/NewReplacement
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} /testbench/dut/hart/lsu/dcache/LRUWriteEn
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WriteEnable}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetValid}
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@ -331,12 +333,10 @@ add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/g
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add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/TLBMiss
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add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/TLBHit
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add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/PhysicalAddress
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add wave -noupdate -expand -group lsu -group dtlb -label {Virtual Address} /testbench/dut/hart/lsu/dmmu/Address
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add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/TLBPageFault
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add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/LoadAccessFaultM
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add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/StoreAccessFaultM
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add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/TLBPAdr
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add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/genblk1/tlb/Address
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add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/genblk1/tlb/PTE
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add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/genblk1/tlb/TLBWrite
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add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/pmachecker/PhysicalAddress
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@ -352,80 +352,12 @@ add wave -noupdate -expand -group lsu -expand -group pmp /testbench/dut/hart/lsu
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add wave -noupdate -expand -group lsu -expand -group pmp /testbench/dut/hart/lsu/dmmu/PMPLoadAccessFaultM
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add wave -noupdate -expand -group lsu -expand -group pmp /testbench/dut/hart/lsu/dmmu/PMPStoreAccessFaultM
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add wave -noupdate -expand -group lsu -expand -group ptwalker -color Gold /testbench/dut/hart/lsu/hptw/genblk1/WalkerState
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add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HCLK
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add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HSELPLIC
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add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HADDR
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add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HWRITE
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add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HREADY
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add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HTRANS
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add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HWDATA
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add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/UARTIntr
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add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/GPIOIntr
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add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HREADPLIC
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add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HRESPPLIC
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add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HREADYPLIC
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add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/ExtIntM
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add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HCLK
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add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HSELGPIO
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add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HADDR
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add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HWDATA
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add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HWRITE
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add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HREADY
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add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HTRANS
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add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HREADGPIO
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add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HRESPGPIO
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add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HREADYGPIO
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add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOPinsIn
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add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOPinsOut
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add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOPinsEn
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add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOIntr
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add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HCLK
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add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HSELCLINT
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add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HADDR
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add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HWRITE
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add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HWDATA
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add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HREADY
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add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HTRANS
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add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HREADCLINT
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add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HRESPCLINT
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add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HREADYCLINT
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add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/MTIME
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add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/MTIMECMP
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add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/TimerIntM
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add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/SwIntM
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add wave -noupdate -group csr /testbench/dut/hart/priv/csr/MIP_REGW
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add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HCLK
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add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HRESETn
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add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HSELUART
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add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HADDR
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add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HWRITE
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add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HWDATA
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add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HREADUART
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add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HRESPUART
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add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HREADYUART
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add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/SIN
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add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/DSRb
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add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/DCDb
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add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/CTSb
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add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/RIb
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add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genblk4/uart/SOUT
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add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genblk4/uart/RTSb
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add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genblk4/uart/DTRb
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add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genblk4/uart/OUT1b
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add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genblk4/uart/OUT2b
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add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genblk4/uart/INTR
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add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genblk4/uart/TXRDYb
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add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genblk4/uart/RXRDYb
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add wave -noupdate -expand -group itlb /testbench/dut/hart/ifu/immu/TLBWrite
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add wave -noupdate -expand -group itlb /testbench/dut/hart/ifu/ITLBMissF
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add wave -noupdate -expand -group itlb /testbench/dut/hart/ifu/immu/PhysicalAddress
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add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HCLK
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add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HSELUART
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add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HADDR
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add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HWRITE
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add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HWDATA
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TreeUpdate [SetDefaultTree]
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WaveRestoreCursors {{Walk read is wrong} {26824 ns} 1} {{page table setup} {8167 ns} 1} {{eviction at wrong adr} {10128 ns} 1} {{Cursor 6} {9967 ns} 0}
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WaveRestoreCursors {{Walk read is wrong} {26824 ns} 1} {{page table setup} {8167 ns} 1} {{eviction at wrong adr} {10128 ns} 1} {{Cursor 6} {7778 ns} 0}
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quietly wave cursor active 4
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configure wave -namecolwidth 250
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configure wave -valuecolwidth 297
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@ -441,4 +373,4 @@ configure wave -griddelta 40
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configure wave -timeline 0
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configure wave -timelineunits ns
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update
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WaveRestoreZoom {9904 ns} {10352 ns}
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WaveRestoreZoom {7636 ns} {7946 ns}
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33
wally-pipelined/src/cache/cacheLRU.sv
vendored
33
wally-pipelined/src/cache/cacheLRU.sv
vendored
@ -62,7 +62,7 @@ module cacheLRU
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assign LRUMask[2] = WayIn[3] | WayIn[2];
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for(index = 0; index < NUMWAYS-1; index++)
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assign LRUOut[index] = LRUEn[index] ? LRUIn[index] : LRUMask[index];
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assign LRUOut[index] = LRUEn[index] ? LRUMask[index] : LRUIn[index];
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assign EncVicWay[1] = LRUIn[2];
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assign EncVicWay[0] = LRUIn[2] ? LRUIn[0] : LRUIn[1];
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@ -73,6 +73,37 @@ module cacheLRU
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end else if (NUMWAYS == 8) begin : EightWay
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// selects
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assign LRUEn[6] = 1'b1;
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assign LRUEn[5] = WayIn[7] | WayIn[6] | WayIn[5] | WayIn[4];
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assign LRUEn[4] = WayIn[7] | WayIn[6];
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assign LRUEn[3] = WayIn[5] | WayIn[4];
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assign LRUEn[2] = WayIn[3] | WayIn[2] | WayIn[1] | WayIn[0];
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assign LRUEn[1] = WayIn[3] | WayIn[2];
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assign LRUEn[0] = WayIn[1] | WayIn[0];
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// mask
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assign LRUMask[6] = WayIn[7] | WayIn[6] | WayIn[5] | WayIn[4];
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assign LRUMask[5] = WayIn[7] | WayIn[6];
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assign LRUMask[4] = WayIn[7];
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assign LRUMask[3] = WayIn[5];
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assign LRUMask[2] = WayIn[3] | WayIn[2];
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assign LRUMask[1] = WayIn[2];
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assign LRUMask[0] = WayIn[0];
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for(index = 0; index < NUMWAYS-1; index++)
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assign LRUOut[index] = LRUEn[index] ? LRUMask[index] : LRUIn[index];
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assign EncVicWay[2] = LRUIn[6];
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assign EncVicWay[1] = LRUIn[6] ? LRUIn[5] : LRUIn[2];
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assign EncVicWay[0] = LRUIn[6] ? LRUIn[5] ? LRUIn[4] : LRUIn[3] :
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LRUIn[2] ? LRUIn[1] : LRUIn[0];
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oneHotDecoder #(3)
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oneHotDecoder(.bin(EncVicWay),
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.decoded({VictimWay[0], VictimWay[1], VictimWay[2], VictimWay[3],
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VictimWay[4], VictimWay[5], VictimWay[6], VictimWay[7]}));
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end
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endgenerate
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