Xavi/cvw
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1685 Commits

Author SHA1 Message Date
David Harris
2bf51362e2 Added synchronizer to reset 2021-10-25 10:05:41 -07:00
bbracker
9b98a499d7 some linux testbench cleanup 2021-10-25 10:04:30 -07:00
Ross Thompson
76bba541a7 Modified the cache's sram model so if it used to synthesize flip flops it terminates the read critical path at the address's input rather than the output read data. 2021-10-24 21:21:49 -05:00
bbracker
9fdfc750eb checkpoint initialization bugfix 2021-10-24 18:39:51 -07:00
bbracker
13763b002a switch linux graphical sim over to Ross's waves 2021-10-24 18:39:23 -07:00
bbracker
fef09e9a5b remove unused scripts 2021-10-24 15:19:03 -07:00
bbracker
09959617c6 update debugger script to new style 2021-10-24 15:18:44 -07:00
bbracker
cc484569cd fix typo 2021-10-24 15:05:00 -07:00
bbracker
046a78a8fc manually resolved git merge conflicts in testbench linux after checkpointing 2021-10-24 15:02:19 -07:00
bbracker
3531a934c9 checkpoint generator bugfix 2021-10-24 14:46:56 -07:00
Ross Thompson
8a51fe76c1 Partial cleanup of unused signals in caches and bpred. 2021-10-24 15:04:20 -05:00
bbracker
c0a7b12f94 or actually needed to reduce expectations of buildroot 2021-10-24 06:59:34 -07:00
bbracker
d3969bb1ba increase regression's expectations of buildroot 2021-10-24 06:50:22 -07:00
bbracker
36b39358c6 add checkpointing to linux testbench 2021-10-24 06:47:35 -07:00
bbracker
d445095f1b revamp linux testvector generation for refactoring checkpoint generation 2021-10-24 06:14:11 -07:00
bbracker
e0b6566cbd buildroot do scripts now compile flops 2021-10-23 23:14:59 -07:00
bbracker
26eead1c77 add W stage signals to linux testbench 2021-10-23 14:00:53 -07:00
bbracker
de6a52f6eb Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-23 13:17:37 -07:00
bbracker
3c0b0987d2 add option for regression to do a partial execution of buildroot 2021-10-23 13:17:30 -07:00
David Harris
200eb453fb wrapping up lint cleanup; many unused signals removed 2021-10-23 12:15:14 -07:00
David Harris
c9e9cd4a60 more lsu/ifu lint cleanup 2021-10-23 12:10:13 -07:00
David Harris
2cfbd888fd more lsu/ifu lint cleanup 2021-10-23 12:00:32 -07:00
David Harris
62a23fe878 lsu/ifu lint cleanup 2021-10-23 11:41:20 -07:00
David Harris
61fdb3d902 random lint cleanup 2021-10-23 11:24:36 -07:00
David Harris
8d9efcbafb IEU cleanup 2021-10-23 11:13:28 -07:00
David Harris
4bf823e063 lint cleanup 2021-10-23 11:03:28 -07:00
David Harris
d570df864f IEU lint cleanup 2021-10-23 10:51:53 -07:00
David Harris
8e516e6391 Lint cleanup from wallypipeliendhart 2021-10-23 10:29:52 -07:00
David Harris
33358d101e Lint cleanup: ahblite, ifu, hart 2021-10-23 10:12:33 -07:00
David Harris
d24bece3a8 Lint cleanup 2021-10-23 09:58:52 -07:00
David Harris
2e796e3da2 lint cleanup: FPU and privileged 2021-10-23 09:41:24 -07:00
David Harris
c316bff15a subword read and csrc lint cleanup 2021-10-23 09:29:15 -07:00
David Harris
28d8f6d5cf FMA and CSRC lint cleanup 2021-10-23 09:20:24 -07:00
David Harris
11b0607e63 Lint cleanup 2021-10-23 09:06:21 -07:00
David Harris
ac1b1bfbb6 update scripts for handling src/*/* subdirectories 2021-10-23 08:54:29 -07:00
David Harris
0dabb6ebd4 lint cleaning and moved files into subdirectories 2021-10-23 08:53:32 -07:00
David Harris
f483e8002a Lint cleanup 2021-10-23 08:39:21 -07:00
David Harris
e2e950ac0f Cleaned up LINT erors 2021-10-23 06:28:49 -07:00
David Harris
4c480a40f6 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-23 06:15:49 -07:00
David Harris
3249d65209 Added -lint flag to vsim. Cleaned some lint errors. Moved lint-wally to regression directory for convenience. 2021-10-23 06:15:26 -07:00
kipmacsaigoren
ef297067e9 removed reduntant definitions for FPU in MISA. 2021-10-22 15:18:25 -05:00
James E. Stine
f6e8e45901 Modify register before fpdivsqrt to be synthesizable for FPGAs and better in tune for ASIC clocking 2021-10-22 13:41:50 -05:00
Katherine Parry
7c7c0f538a put the FMA priority encoders into their own module 2021-10-22 10:03:12 -07:00
James E. Stine
0dcca43f48 Get rid of lint warning - still need more testing though 2021-10-21 15:19:22 -05:00
James E. Stine
dd7dbaa382 Clean up some FPU and add pipelined fpdivsqrt to fpu.sv 2021-10-21 13:52:12 -05:00
James E. Stine
bafb3a983d Fix fpdivsqrt lint error on CPA for convergence 2021-10-20 17:46:13 -05:00
David Harris
ceaf84a3ce removed .* from wallypipeliendsoc 2021-10-20 13:49:18 -07:00
James E. Stine
71b48048da Added pipelined version of fpdivsqrt as well as analysis of fpdivsqrt to cut multiplier down to 60bits. 2021-10-20 12:00:41 -05:00
David Harris
47e19d4caa moved coemark and testsBP to tests 2021-10-20 09:10:06 -07:00
David Harris
23b3d7dbc1 Move tests into subdirectory and moved wavedrom out of project 2021-10-20 09:03:21 -07:00
David Harris
a88af1841f radix 2 SRT checkin 2021-10-19 14:08:16 -07:00
James E. Stine
41010aa418 Some more sanitization but will pass to legal to determine if okay on version - it is substantially different in some ways but not a legal expert on this 2021-10-19 12:09:43 -05:00
James E. Stine
a75abb04bd Modify DW02_multp to properly list the correct number of bits at the output (i.e., 2*WIDTH + 2). 2021-10-19 11:58:06 -05:00
David Harris
3bc985d230 Changed some flops to settable 2021-10-18 17:05:29 -07:00
David Harris
0516ee768b replaced flopenl with flopenr when clearing to 0 2021-10-18 16:53:18 -07:00
David Harris
398337951d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-18 15:44:31 -07:00
David Harris
00d8035836 Fixed multiplier and pointed arch tests to new path in addins 2021-10-18 15:43:59 -07:00
Ross Thompson
cd58a388e4 fixed issues with dc shell not liking modules with parameters without default values. 2021-10-18 17:24:15 -05:00
James E. Stine
37fe5e56a8 Sanitization some more on mult_cs.sv 2021-10-18 05:24:16 -05:00
James E. Stine
d0ab43e4e8 Update some on mult_cs and delete DW02_mult.v 2021-10-18 05:06:49 -05:00
James E. Stine
de7b673e34 Add hacky hand-made carry/save multiplier - will improve 2021-10-16 10:37:29 -05:00
Katherine Parry
c34633804a cvtfp module documented 2021-10-14 15:25:31 -07:00
James E. Stine
c5b99300e7 Clean up some signals - beautification onging 2021-10-14 17:12:00 -05:00
Kip Macsai-Goren
869c35ba1c Fixed typo in imperas64mmu tests causing PMP tests not to run. 2021-10-14 13:42:24 -07:00
Skylar Litz
71397d5db9 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-10-13 15:38:32 -07:00
Skylar Litz
4ca4e13ba2 add StallM signal back to DivStartE control 2021-10-13 15:34:40 -07:00
James E. Stine
1dba57dce7 Update to fpdivsqrt to go on posedge as it should. Also an update to 
individual regression test for TestFloat (still needs some tweaking)
 2021-10-13 17:14:42 -05:00
bbracker
4abc6fc915 change infrastructure to expect only 6.3 million from buildroot 2021-10-12 10:41:15 -07:00
Shreya Sanghai
4424006624 added DESIGN_COMPLIER to forgotten config files 2021-10-12 10:14:04 -07:00
Katherine Parry
b79021a73e lint warnings fixed 2021-10-12 09:45:02 -07:00
Katherine Parry
539d21645f some fpu lint warnings fixed - still working on it 2021-10-11 18:32:03 -07:00
Shreya Sanghai
0acf9fd746 made redunantmul generate DW02_multp for synopsys sythnesis 2021-10-11 11:54:39 -07:00
Shreya Sanghai
84ff2b49c7 actually added redundant mul 2021-10-11 11:29:13 -07:00
David Harris
af7903e1b2 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-11 11:21:39 -07:00
David Harris
1cdc5db75d Extended lint to check rv32/64g (including fpu. Not clean yet. 2021-10-11 11:20:42 -07:00
Shreya Sanghai
a1c9ffdf2b added redundant multiplier 2021-10-11 11:20:12 -07:00
David Harris
ab6a796690 Starting to optimize multiplier 2021-10-11 11:06:07 -07:00
David Harris
f1190b6ceb intdiv cleanup 2021-10-11 08:14:21 -07:00
David Harris
4139f27d10 Divider FSM simplification 2021-10-10 22:24:14 -07:00
David Harris
75c17dc372 Major reorganization of regression and simulation and testbenches 2021-10-10 15:07:51 -07:00
James E. Stine
2b66615812 Update to missing vectors :P and also run_all script. Also made all scripts .sh as technically run using SH 2021-10-10 15:44:01 -05:00
bbracker
13352eccda Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-10 13:12:44 -07:00
bbracker
161767cddd make regression expect what buildroot is actually able to reach 2021-10-10 13:12:36 -07:00
David Harris
a6c6b2b974 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-10 12:26:15 -07:00
David Harris
caf3c2de9b Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-10 12:25:11 -07:00
bbracker
90ccd60790 simplify flopenrc's that didn't actually need to be flopenrc's 2021-10-10 12:25:05 -07:00
David Harris
43d92f2507 Divider cleanup 2021-10-10 12:24:44 -07:00
David Harris
6704e37597 Simplifying divider FSM 2021-10-10 12:21:43 -07:00
David Harris
4deae8019a Simplifying divider FSM 2021-10-10 12:21:36 -07:00
David Harris
2759f1fcb1 Moved & ~StallM from FSM into DivStartE 2021-10-10 11:49:32 -07:00
David Harris
635fe181f8 Moved divide iteration register names to M stage 2021-10-10 11:30:53 -07:00
David Harris
b713b6ca87 Simplified remainder for divide by 0 2021-10-10 11:20:07 -07:00
David Harris
6988c8c37c divider control signal simplificaiton 2021-10-10 10:55:02 -07:00
David Harris
c2bb0324c6 Removed negedge flops from divider 2021-10-10 10:41:13 -07:00
bbracker
2f02287f91 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-10 10:10:06 -07:00
bbracker
a88ae5aaff use correct string formatting function 2021-10-10 10:09:59 -07:00
David Harris
3aa9e088c8 Simplified divider sign handling 2021-10-10 08:35:26 -07:00
David Harris
39bbeefa78 renamed DivStart 2021-10-10 08:32:04 -07:00
David Harris
64ed267825 renamed DivSigned 2021-10-10 08:30:19 -07:00
Katherine Parry
77fe00947e FMA matches diagram and lint warnings fixed 2021-10-09 17:38:10 -07:00