Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main

wally-pipelined/src/cache/cachereplacementpolicy.sv

@@ -25,7 +25,7 @@
 `include "wally-config.vh"
 
 module cachereplacementpolicy
-  #(NUMWAYS, INDEXLEN, OFFSETLEN, NUMLINES)
+  #(parameter NUMWAYS = 4, INDEXLEN = 9, OFFSETLEN = 5, NUMLINES = 128)
   (input logic clk, reset,
    input logic [NUMWAYS-1:0] 			WayHit,
    output logic [NUMWAYS-1:0] 			VictimWay,

wally-pipelined/src/cache/cacheway.sv

@@ -26,7 +26,7 @@
 `include "wally-config.vh"
 
 module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26,
-		   parameter OFFSETLEN, parameter INDEXLEN, parameter DIRTY_BITS = 1) 
+		   parameter OFFSETLEN = 5, parameter INDEXLEN = 9, parameter DIRTY_BITS = 1) 
   (input logic 		       clk,
    input logic 			      reset,
 
@@ -109,6 +109,9 @@ module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26,
   	ValidBits <= {NUMLINES{1'b0}};
     else if (SetValid & (WriteEnable | VDWriteEnable)) ValidBits[WAdr] <= 1'b1;
     else if (ClearValid & (WriteEnable | VDWriteEnable)) ValidBits[WAdr] <= 1'b0;
+  end
+
+  always_ff @(posedge clk) begin
     Valid <= ValidBits[RAdr];
   end
 
@@ -119,6 +122,14 @@ module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26,
   	  DirtyBits <= {NUMLINES{1'b0}};
 	else if (SetDirty & (WriteEnable | VDWriteEnable)) DirtyBits[WAdr] <= 1'b1;
 	else if (ClearDirty & (WriteEnable | VDWriteEnable)) DirtyBits[WAdr] <= 1'b0;
+      end
+    end
+  endgenerate
+
+  // Since this is always updated on a clock edge we cannot include reset.
+  generate
+    if(DIRTY_BITS) begin
+      always_ff @(posedge clk) begin
 	Dirty <= DirtyBits[RAdr];
       end
     end else begin

wally-pipelined/src/mmu/tlbramline.sv

@@ -25,7 +25,7 @@
 
 `include "wally-config.vh"
 
-module tlbramline #(parameter WIDTH)
+module tlbramline #(parameter WIDTH = 22)
   (input  logic             clk, reset,
    input  logic             re, we,
    input  logic [WIDTH-1:0] d,
@@ -37,4 +37,4 @@ module tlbramline #(parameter WIDTH)
    flopenr #(WIDTH) pteflop(clk, reset, we, d, line);
    assign q = re ? line : 0;
    assign PTE_G = line[5]; // send global bit to CAM as part of ASID matching
-endmodule
+endmodule