forked from Github_Repos/cvw
removed .* from wallypipeliendsoc
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3cdac72e96
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ceaf84a3ce
@ -72,9 +72,19 @@ module wallypipelinedsoc (
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logic [31:0] InstrF;
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// instantiate processor and memories
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wallypipelinedhart hart(.*);
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wallypipelinedhart hart(.clk, .reset,
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.PCF, .TimerIntM, .ExtIntM, .SwIntM, .DataAccessFaultM,
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.MTIME_CLINT, .MTIMECMP_CLINT, .rd2,
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.HRDATA, .HREADY, .HRESP, .HCLK, .HRESETn, .HADDR, .HWDATA,
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.HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK,
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.HSELRegions, .HADDRD, .HSIZED, .HWRITED
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);
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// instructions now come from uncore memory. This line can be removed at any time.
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// imem imem(.AdrF(PCF[`XLEN-1:1]), .*); // temporary until uncore memory is finished***
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uncore uncore(.HWDATAIN(HWDATA), .*);
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uncore uncore(.HCLK, .HRESETn,
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.HADDR, .HWDATAIN(HWDATA), .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HRDATAEXT,
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.HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HADDRD, .HSIZED, .HWRITED,
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.TimerIntM, .SwIntM, .ExtIntM, .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, .UARTSin, .UARTSout, .MTIME_CLINT, .MTIMECMP_CLINT
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);
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endmodule
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