lsu/ifu lint cleanup

wally-pipelined/src/ifu/ifu.sv

@@ -100,7 +100,7 @@ module ifu (
   
   logic [`PA_BITS-1:0] PCPFmmu, PCNextFPhys; // used to either truncate or expand PCPF and PCNextF into `PA_BITS width.
   logic [`XLEN+1:0]    PCFExt;
-  logic                ITLBHitF, ISquashBusAccessF;
+  logic                ITLBHitF;
 
   generate
     if (`XLEN==32) begin
@@ -123,13 +123,11 @@ module ifu (
        .TLBFlush(ITLBFlushF),
        .PhysicalAddress(PCPFmmu),
        .TLBMiss(ITLBMissF),
-       .TLBHit(ITLBHitF),
        .TLBPageFault(ITLBInstrPageFaultF),
        .ExecuteAccessF(1'b1), // ***dh -- this should eventually change to only true if an instruction fetch is occurring
        .AtomicAccessM(1'b0),
        .ReadAccessM(1'b0),
        .WriteAccessM(1'b0),
-       .SquashBusAccess(ISquashBusAccessF),
        .LoadAccessFaultM(),
        .StoreAccessFaultM(),
        .DisableTranslation(1'b0),

wally-pipelined/src/lsu/lrsc.sv

@@ -35,7 +35,6 @@ module lrsc
     output logic [1:0]          MemRWMtoDCache,
     input  logic [1:0] 	        AtomicMtoDCache,
     input  logic [`PA_BITS-1:0] MemPAdrM,  // from mmu to dcache
-    output logic                SquashSCM,
     output logic                SquashSCW
 );
   // Handle atomic load reserved / store conditional
@@ -44,6 +43,7 @@ module lrsc
       logic [`PA_BITS-1:2]  ReservationPAdrW;
       logic 		            ReservationValidM, ReservationValidW; 
       logic 		            lrM, scM, WriteAdrMatchM;
+      logic                 SquashSCM;
 
       assign lrM = MemReadM && AtomicMtoDCache[0];
       assign scM = MemRWMtoLRSC[0] && AtomicMtoDCache[0]; 
@@ -59,7 +59,6 @@ module lrsc
       flopenrc #(1) resvldreg(clk, reset, FlushW, lrM, ReservationValidM, ReservationValidW);
       flopenrc #(1) squashreg(clk, reset, FlushW, ~StallWtoDCache, SquashSCM, SquashSCW);
     end else begin // Atomic operations not supported
-      assign SquashSCM = 0;
       assign SquashSCW = 0;
       assign MemRWMtoDCache = MemRWMtoLRSC;
     end

wally-pipelined/src/lsu/lsu.sv

@@ -93,7 +93,6 @@ module lsu
    input 		       var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0] // *** this one especially has a large note attached to it in pmpchecker.
    );
 
-  logic 		       SquashSCM;
   logic 		       DTLBPageFaultM;
   logic            DTLBHitM;
 
@@ -199,14 +198,14 @@ module lsu
        .TLBFlush(DTLBFlushM),
        .PhysicalAddress(MemPAdrM),
        .TLBMiss(DTLBMissM),
-       .TLBHit(DTLBHitM),
+       //.TLBHit(DTLBHitM),
        .TLBPageFault(DTLBPageFaultM),
        .ExecuteAccessF(1'b0),
        //.AtomicAccessM(AtomicMaskedM[1]),
        .AtomicAccessM(1'b0),
        .WriteAccessM(MemRWMtoLRSC[0]),
        .ReadAccessM(MemRWMtoLRSC[1]),
-       .SquashBusAccess(),
+       //.SquashBusAccess(),
        .DisableTranslation(DisableTranslation),
        .InstrAccessFaultF(),
        .Cacheable(CacheableM),
@@ -217,7 +216,7 @@ module lsu
 
   assign MemReadM = MemRWMtoLRSC[1] & ~(ExceptionM | PendingInterruptMtoDCache) & ~DTLBMissM; // & ~NonBusTrapM & ~DTLBMissM & CurrState != STATE_STALLED;
   lrsc lrsc(.clk, .reset, .FlushW, .StallWtoDCache, .MemReadM, .MemRWMtoLRSC, .AtomicMtoDCache, .MemPAdrM,
-            .SquashSCM, .SquashSCW, .MemRWMtoDCache);
+            .SquashSCW, .MemRWMtoDCache);
 
   // *** BUG, this is most likely wrong
   assign CacheableMtoDCache = SelPTW ? 1'b1 : CacheableM;

wally-pipelined/src/mmu/mmu.sv

@@ -67,7 +67,6 @@ module mmu #(parameter TLB_ENTRIES = 8, // number of TLB Entries
   // Physical address outputs
   output logic [`PA_BITS-1:0] PhysicalAddress,
   output logic             TLBMiss,
-  output logic             TLBHit,
   output logic             Cacheable, Idempotent, AtomicAllowed,
 
   // Faults
@@ -77,11 +76,7 @@ module mmu #(parameter TLB_ENTRIES = 8, // number of TLB Entries
   // PMA checker signals
   input  logic             AtomicAccessM, ExecuteAccessF, WriteAccessM, ReadAccessM,
   input  var logic [7:0]   PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0],
-  input  var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0], 
-
-  output logic             SquashBusAccess // *** send to privileged unit
-//  output logic [5:0]       SelRegions
-
+  input  var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0]
 );
 
   logic [`PA_BITS-1:0] TLBPAdr;
@@ -92,6 +87,7 @@ module mmu #(parameter TLB_ENTRIES = 8, // number of TLB Entries
   logic PMALoadAccessFaultM, PMPLoadAccessFaultM;
   logic PMAStoreAccessFaultM, PMPStoreAccessFaultM;
   logic Translate;
+  logic TLBHit;
 
 
   // only instantiate TLB if Virtual Memory is supported
@@ -126,7 +122,7 @@ module mmu #(parameter TLB_ENTRIES = 8, // number of TLB Entries
 
 
   // If TLB miss and translating we want to not have faults from the PMA and PMP checkers.
-  assign SquashBusAccess = PMASquashBusAccess | PMPSquashBusAccess;
+//  assign SquashBusAccess = PMASquashBusAccess | PMPSquashBusAccess;
   assign InstrAccessFaultF = (PMAInstrAccessFaultF | PMPInstrAccessFaultF) & ~(Translate & ~TLBHit);
   assign LoadAccessFaultM = (PMALoadAccessFaultM | PMPLoadAccessFaultM) & ~(Translate & ~TLBHit);
   assign StoreAccessFaultM = (PMAStoreAccessFaultM | PMPStoreAccessFaultM) & ~(Translate & ~TLBHit);  

wally-pipelined/src/privileged/csr.sv

@@ -33,8 +33,8 @@ module csr #(parameter
   UIE_REGW = 12'b0
   ) (
   input  logic             clk, reset,
-  input  logic             FlushD, FlushE, FlushM, FlushW,
-  input  logic             StallD, StallE, StallM, StallW,
+  input  logic             FlushE, FlushM, FlushW,
+  input  logic             StallE, StallM, StallW,
   input  logic [31:0]      InstrM, 
   input  logic [`XLEN-1:0] PCM, SrcAM,
   input  logic             CSRReadM, CSRWriteM, TrapM, MTrapM, STrapM, UTrapM, mretM, sretM, uretM,