James E. Stine f6e8e45901 Modify register before fpdivsqrt to be synthesizable for FPGAs and better in tune for ASIC clocking		2021-10-22 13:41:50 -05:00
..
bin	Added testbench-arch for riscv-arch-test suite	2021-09-08 15:59:40 -04:00
config	added DESIGN_COMPLIER to forgotten config files	2021-10-12 10:14:04 -07:00
fpu-testfloat/FMA/tbgen	FMA matches diagram and lint warnings fixed	2021-10-09 17:38:10 -07:00
linux-testgen	update linker scripts to look for vmlinux files	2021-10-06 16:55:38 -04:00
misc	Clean up MMU code	2021-05-14 07:12:32 -04:00
ppa	Config file for ppa experiments	2021-03-25 10:23:21 -05:00
regression	Update to fpdivsqrt to go on posedge as it should. Also an update to	2021-10-13 17:14:42 -05:00
src	Modify register before fpdivsqrt to be synthesizable for FPGAs and better in tune for ASIC clocking	2021-10-22 13:41:50 -05:00
srt	moved coemark and testsBP to tests	2021-10-20 09:10:06 -07:00
testbench	put the FMA priority encoders into their own module	2021-10-22 10:03:12 -07:00
testgen	mcause test fixes and s-mode interrupt bugfix	2021-06-16 17:37:08 -04:00
lint-wally	Extended lint to check rv32/64g (including fpu. Not clean yet.	2021-10-11 11:20:42 -07:00