forked from Github_Repos/cvw
Starting to optimize multiplier
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@ -27,9 +27,11 @@
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module mul (
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// Execute Stage interface
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input logic clk, reset,
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input logic StallM, FlushM,
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input logic [`XLEN-1:0] SrcAE, SrcBE,
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input logic [2:0] Funct3E,
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output logic [`XLEN*2-1:0] ProdE
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output logic [`XLEN*2-1:0] ProdM
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);
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// Number systems
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@ -46,16 +48,25 @@ module mul (
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// Signed * Unsigned = P' + ( PA - PB)*2^(XLEN-1) - PP*2^(2XLEN-2)
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// Unsigned * Unsigned = P' + ( PA + PB)*2^(XLEN-1) + PP*2^(2XLEN-2)
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logic [`XLEN*2-1:0] PP1, PP2, PP3, PP4;
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logic [`XLEN*2-1:0] PP0E, PP1E, PP2E, PP3E, PP4E;
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logic [`XLEN*2-1:0] PP0M, PP1M, PP2M, PP3M, PP4M;
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logic [`XLEN*2-1:0] Pprime;
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logic [`XLEN-2:0] PA, PB;
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logic PP;
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logic MULH, MULHSU, MULHU;
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logic [`XLEN-1:0] Aprime, Bprime;
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//////////////////////////////
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// Execute Stage: Compute partial products
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//////////////////////////////
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// portions of product
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assign Pprime = {1'b0, SrcAE[`XLEN-2:0]} * {1'b0, SrcBE[`XLEN-2:0]};
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//assign Pprime = {1'b0, SrcAE[`XLEN-2:0]} * {1'b0, SrcBE[`XLEN-2:0]};
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// *** assumes unsigned multiplication
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assign Aprime = {1'b0, SrcAE[`XLEN-2:0]};
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assign Bprime = {1'b0, SrcBE[`XLEN-2:0]};
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DW02_multp #(`XLEN, `XLEN, 2*`XLEN) bigmul(.a(Aprime), .b(Bprime), .tc(1'b0), .out0(PP0E), .out1(PP1E));
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// DW02_multp #((`XLEN-1), (`XLEN-1), 2*(`XLEN-1)) multp_dw( .a(SrcAE[`XLEN-2:0]), .b(SrcBE[`XLEN-2:0]), .tc(1'b0), .out0(Pprime0), .out1(Pprime1) );
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assign PA = {(`XLEN-1){SrcAE[`XLEN-1]}} & SrcBE[`XLEN-2:0];
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assign PB = {(`XLEN-1){SrcBE[`XLEN-1]}} & SrcAE[`XLEN-2:0];
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@ -67,16 +78,25 @@ module mul (
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// assign MULHU = (Funct3E == 2'b11); // signal unused
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// Handle signs
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assign PP1 = Pprime; // same for all flavors
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assign PP2 = {2'b00, (MULH | MULHSU) ? ~PA : PA, {(`XLEN-1){1'b0}}};
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assign PP3 = {2'b00, (MULH) ? ~PB : PB, {(`XLEN-1){1'b0}}};
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// assign PP0E = 0;
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// assign PP1E = Pprime; // same for all flavors
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assign PP2E = {2'b00, (MULH | MULHSU) ? ~PA : PA, {(`XLEN-1){1'b0}}};
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assign PP3E = {2'b00, (MULH) ? ~PB : PB, {(`XLEN-1){1'b0}}};
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always_comb
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if (MULH) PP4 = {1'b1, PP, {(`XLEN-3){1'b0}}, 1'b1, {(`XLEN){1'b0}}};
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else if (MULHSU) PP4 = {1'b1, ~PP, {(`XLEN-2){1'b0}}, 1'b1, {(`XLEN-1){1'b0}}};
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else PP4 = {1'b0, PP, {(`XLEN*2-2){1'b0}}};
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if (MULH) PP4E = {1'b1, PP, {(`XLEN-3){1'b0}}, 1'b1, {(`XLEN){1'b0}}};
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else if (MULHSU) PP4E = {1'b1, ~PP, {(`XLEN-2){1'b0}}, 1'b1, {(`XLEN-1){1'b0}}};
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else PP4E = {1'b0, PP, {(`XLEN*2-2){1'b0}}};
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// ***Put register before this final addition
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assign ProdE = PP1 + PP2 + PP3 + PP4; //SrcAE * SrcBE;
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// assign ProdE = Pprime0 + Pprime1 + PP2 + PP3 + PP4; //SrcAE * SrcBE;
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//////////////////////////////
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// Memory Stage: Sum partial proudcts
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//////////////////////////////
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flopenrc #(`XLEN*2) PP0Reg(clk, reset, FlushM, ~StallM, PP0E, PP0M);
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flopenrc #(`XLEN*2) PP1Reg(clk, reset, FlushM, ~StallM, PP1E, PP1M);
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flopenrc #(`XLEN*2) PP2Reg(clk, reset, FlushM, ~StallM, PP2E, PP2M);
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flopenrc #(`XLEN*2) PP3Reg(clk, reset, FlushM, ~StallM, PP3E, PP3M);
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flopenrc #(`XLEN*2) PP4Reg(clk, reset, FlushM, ~StallM, PP4E, PP4M);
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assign ProdM = PP0M + PP1M + PP2M + PP3M + PP4M; //SrcAE * SrcBE;
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endmodule
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@ -43,10 +43,10 @@ module muldiv (
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generate
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if (`M_SUPPORTED) begin
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logic [`XLEN-1:0] MulDivResultE, MulDivResultM;
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logic [`XLEN-1:0] MulDivResultM;
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logic [`XLEN-1:0] PrelimResultM;
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logic [`XLEN-1:0] QuotM, RemM;
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logic [`XLEN*2-1:0] ProdE, ProdM;
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logic [`XLEN*2-1:0] ProdM;
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logic DivE;
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logic DivSignedE;
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@ -54,7 +54,6 @@ module muldiv (
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// Multiplier
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mul mul(.*);
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flopenrc #(`XLEN*2) ProdMReg(clk, reset, FlushM, ~StallM, ProdE, ProdM);
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// Divide
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// Start a divide when a new division instruction is received and the divider isn't already busy or finishing
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