forked from Github_Repos/cvw
remove unused scripts
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09959617c6
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#grep '=>.*csr' $1 | rev | cut -d' ' -f1 | rev | tee >(cut -d',' -f1) | cut -d',' -f2 | grep -Ev 'a[0-7]|t[0-6]|zero|[0-8]' | sort | uniq | paste -s -d, -
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grep 'csr' /mnt/scratch/riscv_decodepc_threads/riscv_decodepc.txt.disassembly | rev | cut -d' ' -f1 | rev | tee >(cut -d',' -f1 | sort -u) >(cut -d',' -f2 | sort -u) | (cut -d',' -f3 | sort -u) | sort -u | paste -s -d, -
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#! /usr/bin/python3
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import sys, fileinput
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sys.stderr.write("reminder: fix_csrs.py is nothing but hardcoded hackery to combat QEMU's faulty printing")
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csrs = ['fcsr','mcause','mcounteren','medeleg','mepc','mhartid','mideleg','mie','mip','misa','mscratch','mstatus','mtval','mtvec','pmpaddr0','pmpcfg0','satp','scause','scounteren','sepc','sie','sscratch','sstatus','stval','stvec']
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# just for now, since these CSRs aren't yet ready to be checked in testbench-linux
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list(map(csrs.remove, ['fcsr','mhartid','pmpcfg0','pmpaddr0','mip']))
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output_path = sys.argv[1]+'/'
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print(f'output dir: {output_path}')
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count = 0
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csr = ''
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with open('{}parsedCSRs.txt'.format(output_path), 'w') as fixedCSRs:
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with open('{}/intermediate-outputs/unfixedParsedCSRs.txt'.format(output_path), 'r') as rawCSRs:
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for l in rawCSRs:
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fixedCSRs.write(l)
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count += 1
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if '---' in l:
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count = 0
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if (count%2 == 1): # every other line is CSR name
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csr = l
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else:
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if ('stval' in csr) and ('8020007e' in l):
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print('Adding stvec vector')
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fixedCSRs.write('stvec\n')
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fixedCSRs.write('ffffffff800000b0\n')
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# Oftentimes this script runs so long you'll go to sleep.
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# But you don't want the script to die when your computer goes to sleep.
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# So consider invoking this with nohup (i.e. "nohup ./logAllBuildroot.sh")
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# You can run "tail -f nohup.out" to see what would've
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# outputted to the terminal if you didn't use nohup
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customQemu="/courses/e190ax/qemu_sim/rv64_initrd/qemu_experimental/qemu/build/qemu-system-riscv64"
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#customQemu="qemu-system-riscv64"
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imageDir="../buildroot-image-output"
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intermedDir="../linux-testvectors/intermediate-outputs"
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outDir="../linux-testvectors"
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# - Logs info needed by buildroot testbench
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($customQemu -M virt -nographic -bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio -d nochain,cpu,in_asm -serial /dev/null -singlestep -gdb tcp::1236 -S 2>&1 >/dev/null | ./parse_qemu.py | ./parse_gdb_output.py "$outDir") & riscv64-unknown-elf-gdb -x gdbinit_qemulog
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./fix_csrs.py "$outDir"
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./combineGDBs.py && cat gdbcombined.txt | ./parse_gdb_output.py "/courses/e190ax/busybear_boot_new/"
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#! /usr/bin/python3
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import sys, fileinput
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sys.stderr.write("reminder: parse_gdb_output.py takes input from stdin\n")
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csrs = ['fcsr','mcause','mcounteren','medeleg','mepc','mhartid','mideleg','mie','mip','misa','mscratch','mstatus','mtval','mtvec','pmpaddr0','pmpcfg0','satp','scause','scounteren','sepc','sie','sscratch','sstatus','stval','stvec']
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# just for now, since these CSRs aren't yet ready to be checked in testbench-linux
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list(map(csrs.remove, ['fcsr','mhartid','pmpcfg0','pmpaddr0','mip']))
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#output_path = '/courses/e190ax/busybear_boot_new/'
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#output_path = '/courses/e190ax/buildroot_boot/'
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output_path = sys.argv[1]+'/'
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print(f'output dir: {output_path}')
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instrs = -1
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try:
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with open('{}parsedPC.txt'.format(output_path), 'w') as wPC:
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with open('{}parsedRegs.txt'.format(output_path), 'w') as wReg:
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with open('{}parsedMemRead.txt'.format(output_path), 'w') as wMem:
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with open('{}parsedMemWrite.txt'.format(output_path), 'w') as wMemW:
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with open('{}/intermediate-outputs/unfixedParsedCSRs.txt'.format(output_path), 'w') as wCSRs:
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firstCSR = True
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curCSRs = {}
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lastRead = ''
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currentRead = ''
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readOffset = ''
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lastReadLoc = ''
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readType = ''
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lastReadType = ''
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readLoc = ''
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lineOffset = -1
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lastRegs = ''
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curRegs = ''
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storeReg = ''
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storeOffset = ''
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storeLoc = ''
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storeAMO = ''
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lastAMO = ''
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lastStoreReg = ''
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lastStoreLoc = ''
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for l in fileinput.input('-'):
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l = l.split("#")[0].rstrip()
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if l.startswith('=>'):
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# Begin new instruction
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instrs += 1
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storeAMO = ''
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if instrs % 10000 == 0:
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print(instrs,flush=True)
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# Instr in human assembly
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wPC.write('{} ***\n'.format(' '.join(l.split(':')[1].split()[0:2])))
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if '\tld' in l or '\tlw' in l or '\tlh' in l or '\tlb' in l:
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currentRead = l.split()[-1].split(',')[0]
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if len(l.split()[-1].split(',')) < 2:
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print(l)
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readOffset = l.split()[-1].split(',')[1].split('(')[0]
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readLoc = l.split()[-1].split(',')[1].split('(')[1][:-1]
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readType = l.split()[-2]
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if 'amo' in l:
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currentRead = l.split()[-1].split(',')[0]
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readOffset = "0"
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readLoc = l.split()[-1].split('(')[1][:-1]
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readType = l.split()[-2]
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storeOffset = "0"
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storeLoc = readLoc
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storeReg = l.split()[-1].split(',')[1]
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storeAMO = l.split()[-2]
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if '\tlr' in l:
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currentRead = l.split()[-1].split(',')[0]
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readOffset = "0"
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readLoc = l.split()[-1].split('(')[1][:-1]
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readType = "0" # *** I don't see that readType or lastReadType are ever used; we can probably get rid of them
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if '\tsc' in l:
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storeOffset = "0"
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storeLoc = l.split()[-1].split('(')[1][:-1]
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storeReg = l.split()[-1].split(',')[1]
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if '\tsd' in l or '\tsw' in l or '\tsh' in l or '\tsb' in l:
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s = l.split('#')[0].split()[-1]
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storeReg = s.split(',')[0]
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if len(s.split(',')) < 2:
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print(s)
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print(l)
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if len(s.split(',')[1].split('(')) < 1:
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print(s)
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print(l)
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storeOffset = s.split(',')[1].split('(')[0]
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storeLoc = s.split(',')[1].split('(')[1][:-1]
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lineOffset = 0
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elif lineOffset != -1:
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lineOffset += 1
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if lineOffset == 1:
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# Instr in hex comes one line after the instruction
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wPC.write('{}\n'.format(l.split()[-1][2:]))
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# As well as instr address
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wPC.write('{}\n'.format(l.split()[0][2:].strip(":")))
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elif lineOffset <= (1+32):
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# Next 32 lines are the Register File
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if lastRead == l.split()[0]:
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readData = int(l.split()[1][2:], 16)
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#readData <<= (8 * (lastReadLoc % 8)) <-- this was used to make byte and half-word instructions match what the bus unit sees in RV64. However, it is no longer needed because the testvectors are now compared against what the hart sees (not what the bus unit sees).
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wMem.write('{:x}\n'.format(readData))
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if readLoc == l.split()[0]:
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readLoc = l.split()[1][2:]
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if storeReg == l.split()[0]:
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storeReg = l.split()[1]
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if storeLoc == l.split()[0]:
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storeLoc = l.split()[1][2:]
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if lineOffset > (1+1):
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# Start logging x1 onwards (we don't care about x0)
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curRegs += '{}\n'.format(l.split()[1][2:])
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#elif "pc" in l:
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# wPC.write('{}\n'.format(l.split()[1][2:]))
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if any([csr == l.split()[0] for csr in csrs]):
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if l.split()[0] in curCSRs:
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if curCSRs[l.split()[0]] != l.split()[1]:
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if firstCSR:
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wCSRs.write('---\n')
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firstCSR = False
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wCSRs.write('{}\n{}\n'.format(l.split()[0], l.split()[1][2:]))
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else:
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wCSRs.write('{}\n{}\n'.format(l.split()[0], l.split()[1][2:]))
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curCSRs[l.split()[0]] = l.split()[1]
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if '-----' in l: # end of each cycle
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if curRegs != lastRegs:
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if lastRegs == '':
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wReg.write(curRegs)
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else:
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for i in range(32):
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if curRegs.split('\n')[i] != lastRegs.split('\n')[i]:
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wReg.write('{}\n'.format(i+1))
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wReg.write('{}\n'.format(curRegs.split('\n')[i]))
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break
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lastRegs = curRegs
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if lastAMO != '':
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if 'amoadd' in lastAMO:
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lastStoreReg = hex(int(lastStoreReg[2:], 16) + readData)[2:]
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elif 'amoand' in lastAMO:
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lastStoreReg = hex(int(lastStoreReg[2:], 16) & readData)[2:]
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elif 'amoor' in lastAMO:
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lastStoreReg = hex(int(lastStoreReg[2:], 16) | readData)[2:]
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elif 'amoswap' in lastAMO:
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lastStoreReg = hex(int(lastStoreReg[2:], 16))[2:]
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else:
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print(lastAMO)
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exit()
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#print('lastStoreReg {}\n'.format(lastStoreReg))
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#print('lastStoreLoc '+str(lastStoreLoc))
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wMemW.write('{}\n'.format(lastStoreReg))
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wMemW.write('{:x}\n'.format(int(lastStoreLoc, 16)))
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if storeReg != '' and storeOffset != '' and storeLoc != '' and storeAMO == '':
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storeLocOffset = int(storeOffset,10) + int(storeLoc, 16)
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#wMemW.write('{:x}\n'.format(int(storeReg, 16) << (8 * (storeLocOffset % 8))))
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wMemW.write('{}\n'.format(storeReg[2:]))
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wMemW.write('{:x}\n'.format(storeLocOffset))
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if readOffset != '' and readLoc != '':
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wMem.write('{:x}\n'.format(int(readOffset,10) + int(readLoc, 16)))
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lastReadLoc = int(readOffset,10) + int(readLoc, 16)
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lastReadType = readType
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readOffset = ''
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readLoc = ''
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curRegs = ''
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lineOffset = -1
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lastRead = currentRead
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currentRead = ''
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lastStoreReg = storeReg
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lastStoreLoc = storeLoc
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storeReg = ''
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storeOffset = ''
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storeLoc = ''
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lastAMO = storeAMO
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except (FileNotFoundError):
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print('please give gdb output file as argument')
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#!/bin/bash
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source /cad/riscv/OVP/Imperas.20200630/bin/setup.sh
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setupImperas /cad/riscv/OVP/Imperas.20200630 -m32
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source /cad/riscv/OVP/Imperas.20200630/bin/switchRuntime.sh 2>/dev/null
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echo 1 | switchRuntimeImperas
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source /cad/riscv/OVP/Imperas.20200630/bin/switchISS.sh 2>/dev/null
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echo 1 | switchISSImperas
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#!/bin/bash
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sh /cad/riscv/OVP/Imperas.20200630/Demo/Platforms/riscv_RV64GC_Virtio_Linux/harness/RUN_Virtio_Linux.sh --gdbconsole --gdbinit /mnt/scratch/riscv_testbench/gdbinit
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set pagination off
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set logging overwrite on
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set logging redirect on
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set logging file /mnt/scratch/riscv_testbench/riscv_boot_regs.txt
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set logging on
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x/i $pc
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x/x $pc
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info all-registers
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while ($pc != 0xffffffe000018fa4)
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si
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x/i $pc
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x/x $pc
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info all-registers
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end
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set logging off
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@ -1,23 +0,0 @@
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set pagination off
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target extended-remote :1235
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set logging overwrite on
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set logging redirect on
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printf "Creating bootmemGDB.txt\n"
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set logging file ../linux-testvectors/intermediate-outputs/bootmemGDB.txt
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set logging on
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x/4096xb 0x1000
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set logging off
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printf "Creating bootmem_untrimmed_GDB.txt\n"
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printf "Warning - please verify that the second half of bootmem_untrimmed_GDB.txt is all 0s\n"
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set logging file ../linux-testvectors/intermediate-outputs/bootmem_untrimmed_GDB.txt
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set logging on
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x/8192xb 0x1000
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set logging off
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printf "Creating ramGDB.txt\n"
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set logging file ../linux-testvectors/intermediate-outputs/ramGDB.txt
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set logging on
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x/134217728xb 0x80000000
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set logging off
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set confirm off
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kill
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q
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