forked from Github_Repos/cvw
update scripts for handling src/*/* subdirectories
This commit is contained in:
David Harris
parent
0dabb6ebd4
commit
ac1b1bfbb6
@ -7,7 +7,7 @@ verilator=`which verilator`
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basepath=$(dirname $0)/..
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for config in rv64g rv32g; do
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echo "$config linting..."
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if !($verilator --lint-only --Wall "$@" --top-module wallypipelinedsoc "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/*/*.sv --relative-includes); then
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if !($verilator --lint-only --Wall "$@" --top-module wallypipelinedsoc "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes); then
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echo "Exiting after $config lint due to errors or warnings"
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exit 1
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fi
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@ -32,7 +32,7 @@ vlib work_${1}_${2}
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# default to config/rv64ic, but allow this to be overridden at the command line. For example:
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# do wally-pipelined-batch.do ../config/rv32ic rv32ic
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vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583
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vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
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# start and run simulation
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# remove +acc flag for faster sim during regressions if there is no need to access internal signals
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@ -37,7 +37,7 @@ vlib work
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#}
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# start and run simulation
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# remove +acc flag for faster sim during regressions if there is no need to access internal signals
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vlog -lint +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583
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vlog -lint +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
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vopt +acc work.testbench -G TEST=$2 -o workopt
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vsim workopt
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@ -46,7 +46,7 @@ module cachereplacementpolicy
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always_ff @(posedge clk, posedge reset) begin
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if (reset) begin
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for(int index = 0; index < NUMLINES; index++)
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ReplacementBits[index] <= '0;
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ReplacementBits[index] = '0;
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end else begin
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BlockReplacementBits <= ReplacementBits[RAdr];
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if (LRUWriteEn) begin
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@ -1,123 +0,0 @@
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///////////////////////////////////////////
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// flop.sv
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//
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// Written: David_Harris@hmc.edu 9 January 2021
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// Modified:
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//
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// Purpose: arious flavors of flip-flops
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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/* verilator lint_off DECLFILENAME */
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// ordinary flip-flop
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module flop #(parameter WIDTH = 8) (
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input logic clk,
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input logic [WIDTH-1:0] d,
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output logic [WIDTH-1:0] q);
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always_ff @(posedge clk)
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q <= #1 d;
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endmodule
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// flop with asynchronous reset
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module flopr #(parameter WIDTH = 8) (
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input logic clk, reset,
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input logic [WIDTH-1:0] d,
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output logic [WIDTH-1:0] q);
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always_ff @(posedge clk, posedge reset)
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if (reset) q <= #1 0;
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else q <= #1 d;
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endmodule
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// flop with enable
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module flopen #(parameter WIDTH = 8) (
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input logic clk, en,
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input logic [WIDTH-1:0] d,
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output logic [WIDTH-1:0] q);
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always_ff @(posedge clk)
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if (en) q <= #1 d;
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endmodule
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// flop with enable, asynchronous reset, synchronous clear
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module flopenrc #(parameter WIDTH = 8) (
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input logic clk, reset, clear, en,
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input logic [WIDTH-1:0] d,
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output logic [WIDTH-1:0] q);
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always_ff @(posedge clk, posedge reset)
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if (reset) q <= #1 0;
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else if (en)
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if (clear) q <= #1 0;
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else q <= #1 d;
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endmodule
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// flop with enable, asynchronous reset
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module flopenr #(parameter WIDTH = 8) (
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input logic clk, reset, en,
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input logic [WIDTH-1:0] d,
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output logic [WIDTH-1:0] q);
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always_ff @(posedge clk, posedge reset)
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if (reset) q <= #1 0;
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else if (en) q <= #1 d;
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endmodule
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// flop with enable, asynchronous set
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module flopens #(parameter WIDTH = 8) (
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input logic clk, set, en,
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input logic [WIDTH-1:0] d,
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output logic [WIDTH-1:0] q);
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always_ff @(posedge clk, posedge set)
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if (set) q <= #1 1;
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else if (en) q <= #1 d;
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endmodule
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// flop with enable, asynchronous load
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module flopenl #(parameter WIDTH = 8, parameter type TYPE=logic [WIDTH-1:0]) (
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input logic clk, load, en,
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input TYPE d,
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input TYPE val,
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output TYPE q);
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always_ff @(posedge clk, posedge load)
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if (load) q <= #1 val;
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else if (en) q <= #1 d;
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endmodule
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// flop with asynchronous reset, synchronous clear
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module floprc #(parameter WIDTH = 8) (
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input logic clk,
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input logic reset,
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input logic clear,
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input logic [WIDTH-1:0] d,
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output logic [WIDTH-1:0] q);
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always_ff @(posedge clk, posedge reset)
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if (reset) q <= #1 0;
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else
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if (clear) q <= #1 0;
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else q <= #1 d;
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endmodule
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/* verilator lint_on DECLFILENAME */
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