Xavi/cvw
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256 Commits

Author SHA1 Message Date
David Harris
e4c5754b3a Made simple RV64 configuration be RV64i. Eliminated rv64ic and rv64fp. Fixed some bugs related to new width 2022-10-10 09:10:55 -07:00
Ross Thompson
382ccf74a5 Cleaned up the new muxes to select between IROM/ICACHE/BUS and DTIM/DCACHE/BUS. 2022-10-05 15:46:53 -05:00
Ross Thompson
62951ec653 Fixed wally32e. 2022-10-05 15:37:01 -05:00
Ross Thompson
2e578eb8d8 Fixed bug with combined dtim+bus. 2022-10-05 15:16:01 -05:00
Ross Thompson
b52ab91028 Possibly have working dtim + bus config. 2022-10-05 15:08:20 -05:00
Ross Thompson
68aa1434b4 Modified the LSU and IFU to allow concurrent DTIM/DCACHE+BUS and IROM/ICACHE+BUS. 
Don't use this commit as the rv32i tests are not passing.
 2022-10-05 14:51:02 -05:00
Ross Thompson
638e506d0b Hmm. the icache and ifu didn't have a CommittedF signals going back to the privileged unit. They probably should. If an interrupt occurred during the middle of an instruction fetch icache miss I think it would corrupt the icache. 2022-09-28 17:39:51 -05:00
Ross Thompson
dcc00ef4b3 Renamed RW signals through the caches, bus interfaces, and IFU/LSU. 
CPU to $ is called LSURWM or IFURWF.
CPU to Bus is called BusRW
$ to Bus is called CacheBusRW.
 2022-09-23 11:46:53 -05:00
Ross Thompson
29087812e1 Solved the sram write first / read first issue. Works correctly with read first now. 2022-09-22 14:16:26 -05:00
Ross Thompson
cd5b8be78f Cleaned up the IFU and LSU around dtim and irom address calculation. 2022-09-21 18:23:56 -05:00
Ross Thompson
c73fae8a96 Merge branch 'tempMain' into main 2022-09-20 13:57:38 -05:00
Ross Thompson
b2f4d4aaa7 Added chip enables to sram. 2022-09-20 10:49:14 -05:00
Ross Thompson
7470bf7c7c Added comment. 2022-09-20 09:49:53 -05:00
Ross Thompson
0fb45cffa1 Removed NonIROM and NonDTIM select signals from IFU and LSU. 2022-09-17 22:01:03 -05:00
Ross Thompson
cc1ba84637 Found the ahb burst bug. 
We had instruction fetches fixed HSIZE = 2 (4 bytes) for all requests.  It should be HSIZE = 3 (8 bytes) for cache fetches and 4 for uncached reads.  The reason this worked for non burst is the DDR4 memory controller returns the full double word even for 4 byte reads.  In burst mode the second beat ending up pointing to the next 4 bytes rather than the next 8 bytes.
 2022-09-17 20:30:01 -05:00
David Harris
a7b5a0419a Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-09-15 12:49:21 -07:00
David Harris
aa1f3ca2be renamed endianswap 2022-09-15 12:49:18 -07:00
Ross Thompson
4c8ae8b421 Fixed subword read to work with bigendian. 2022-09-15 14:08:04 -05:00
Ross Thompson
40e7d2648f Renamed signals in the LSU. 2022-09-13 11:47:39 -05:00
Ross Thompson
8618045bf2 Optimization. Able to remove hptw address muxes from the E stage. 2022-09-08 15:51:18 -05:00
Ross Thompson
ae4a55471d Oups fixed order of ending swap with mux between cache and fetch buffer. 2022-09-07 16:29:47 -05:00
Ross Thompson
3e540a3ca3 Possible fix to AHB burst eviction bug. If HREADY went low during a burst seq the next data phase would only last 1 cycle. 2022-09-02 19:58:41 -05:00
Ross Thompson
83c427c5b5 clean up subword write. 2022-09-01 17:55:19 -05:00
Ross Thompson
5b4e744972 marked possible improvement to ahb bus fsms. 2022-08-31 23:57:08 -05:00
Ross Thompson
ab4c75cbf5 More renaming. 2022-08-31 14:49:08 -05:00
Ross Thompson
6e85f850a4 Moved files. 
Encapsulated ahbinterface.
 2022-08-31 14:45:01 -05:00
Ross Thompson
fcd1465de1 Renamed AHBCachebusdp to abhcacheinterface. 2022-08-31 14:12:19 -05:00
Ross Thompson
1663f571ed More Cleanup. 2022-08-31 11:21:02 -05:00
Ross Thompson
68e54977fe More cleanup. 2022-08-31 11:12:38 -05:00
Ross Thompson
1c248e5164 Removed old signals. 2022-08-31 09:50:39 -05:00
Ross Thompson
5b8f888e21 Maybe fixed it? 2022-08-30 18:08:34 -05:00
Ross Thompson
96793d15c0 more progress. 2022-08-30 17:32:32 -05:00
Ross Thompson
63a824cca1 More progress. 2022-08-30 15:27:19 -05:00
Ross Thompson
a532eb61ba Progress. 2022-08-30 14:17:00 -05:00
Ross Thompson
c8a5d61cbb new cache bus fsm not working but lints. 
Forgot a few files in the last commit.
 2022-08-30 10:58:07 -05:00
Ross Thompson
5eb1fff27d Have a rough working multi manager! 2022-08-29 17:11:27 -05:00
Ross Thompson
4f40bd07c3 Modified rv32e configuration to use a true ahb bus interface in the lsu and ifu. 2022-08-29 17:04:53 -05:00
Ross Thompson
4d7b905806 Part way through the updated bus fsm for direct AHB in lsu/ifu + multi-manager. 2022-08-29 13:01:24 -05:00
Ross Thompson
40cf4a9ea9 Typo. 2022-08-29 11:40:35 -05:00
Ross Thompson
9a7c7e8398 Added comments about planned changes. 2022-08-29 09:48:00 -05:00
Ross Thompson
35d0b759d1 Removed ignore request from busfsm. 2022-08-28 21:12:27 -05:00
Ross Thompson
dd00474956 Created two new pma regions for dtim and irom. 2022-08-28 13:50:50 -05:00
Ross Thompson
99e0e5c817 Possible fix. 2022-08-28 13:10:47 -05:00
Ross Thompson
5e77b1bd2b Partial fix to bus + dtim. 2022-08-27 23:44:17 -05:00
David Harris
35d0a951d2 Preliminary work to make DTIM and Bus compatible. Not yet working because accesses to bus are causing illegal address faults on the bus. 2022-08-27 20:31:09 -07:00
David Harris
3959902c5b Adding decoding for dtim. Added rv32ic_wally32periph test, which should hang until decoder overrides bus 2022-08-27 05:31:56 -07:00
David Harris
6409548c8b Replaced DTIM and IROM with DTIM_SUPPORTED, IROM_SUPPORTED, and base and range for each 2022-08-26 20:26:12 -07:00
David Harris
906f6f2990 Renamed DMEM to DTIM and added checks about compatibility of DTIM/IROM and virtmem 2022-08-26 20:12:03 -07:00
David Harris
841eae58ca Fixed endian swapping on bus only 2022-08-26 19:58:04 -07:00
David Harris
af2e71046e Fixed rv32e LSU and IFU issues 2022-08-25 20:02:38 -07:00
David Harris
8cbdbb1c38 lsu simplification 2022-08-25 18:52:42 -07:00
David Harris
dc52f55aa6 Removed unused signals 2022-08-25 18:34:39 -07:00
David Harris
50826c0b61 Removed unused signals 2022-08-25 18:30:46 -07:00
David Harris
bb4ae908db Removed CacheBusAck 2022-08-25 18:17:34 -07:00
David Harris
85b5587678 Removed SelUncachedAdr 2022-08-25 18:15:59 -07:00
David Harris
555083b0c3 Removed Cache_Enabled 2022-08-25 18:13:34 -07:00
David Harris
de9ec7cc2e Removed CacheFetchLine and CacheWriteLine 2022-08-25 18:10:15 -07:00
David Harris
7eae6765df Removed wordcount 2022-08-25 18:04:49 -07:00
David Harris
0b918d6916 Separated busdp for cache from simpler logic for no cache 2022-08-25 17:54:04 -07:00
David Harris
5c1934208a Simplified swbytemask 2022-08-25 17:32:16 -07:00
Ross Thompson
ad3e632119 Almost fixed issues with irom and dtim address selection. 2022-08-25 15:52:25 -05:00
Ross Thompson
502eb0f5d1 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-25 14:40:52 -05:00
David Harris
d7be94fab2 Cleaned up SelBusWord 2022-08-25 11:18:13 -07:00
David Harris
7a129af9ad Removed M sufix from busdp signals 2022-08-25 11:13:01 -07:00
David Harris
84ba62a04c Renamed LSUFunct3M to Funct3 in busdp 2022-08-25 11:08:12 -07:00
David Harris
78618f5fc0 Renaming LSU signals from busdp 2022-08-25 11:05:10 -07:00
David Harris
cd02c894df renamed BusBuffer to FetchBuffer 2022-08-25 10:44:39 -07:00
David Harris
5dc4fb757a Continued busdp/ebu simplification 2022-08-25 10:20:02 -07:00
David Harris
89860588b8 Renamed AHB signals coming out of LSU to LSH_<AHBNAME> 2022-08-25 09:52:08 -07:00
Ross Thompson
bd9401179d BROKEN. Don't use this commit. 
Issue running cacheless with bus.
 2022-08-25 11:02:46 -05:00
David Harris
4ecdbb308a Renamed DCache to Cache in busdp/busfsm signal interface 2022-08-25 06:21:22 -07:00
David Harris
a3828420c0 Replaced dtim with rom-based IROM in IFU. Moved cache control signals out of DTIM and IROM 2022-08-25 04:06:27 -07:00
David Harris
fe3147806d removed simpleram and modified dtim to use bram1p1rw 2022-08-25 03:39:57 -07:00
Ross Thompson
b650d7e05a Renamed RAM to UNCORE_RAM. 2022-08-24 18:09:07 -05:00
Ross Thompson
c6927d2ace Modified the lsu/ifu memory configurations. 2022-08-24 12:35:15 -05:00
David Harris
27cca2e3fd Fixed LSU typos 2022-08-23 10:23:08 -07:00
Ross Thompson
b9fadc11c3 Replaced LSU data replication with 0 extention. 2022-08-23 10:43:47 -05:00
Ross Thompson
cd0da2e3b3 Updated the names of the *WriteDataM inside the LSU to more meaningful names. 
Moved the FWriteDataMux so that the bus and dtim both get fpu stores.
Modified the PMA to disallow double sized reads when XLEN=32.
 2022-08-23 10:34:39 -05:00
David Harris
7c91ed38a3 LSU minor edits 2022-08-23 07:35:47 -07:00
David Harris
34eece10b8 Finished FPU-LSU interface cleanup 2022-08-22 13:43:04 -07:00
David Harris
bf54c1c868 Simplified FPU-LSU interface to skip IEU 2022-08-22 13:29:20 -07:00
Ross Thompson
21526957cf Updated fpga test bench. 
Solved read delay cache bug.  Introduced during cache optimizations.
 2022-08-21 15:59:54 -05:00
Ross Thompson
96d6218078 Possible reduction of ignorerequest. 2022-08-19 18:07:44 -05:00
Ross Thompson
5301444a61 Changed signal names. 2022-08-17 16:12:04 -05:00
Ross Thompson
970a90dd72 Better name for LSUBusWriteCrit. Changed to SelLSUBusWord. 2022-08-17 16:09:20 -05:00
Ross Thompson
f7e64fcd69 Fixed fstore2 in cache? 2022-08-01 22:04:44 -05:00
Ross Thompson
b8356c7449 Replaced swbytemask with swbytemaskword (1 liner). Credit to David Harris. 2022-08-01 21:12:25 -05:00
Ross Thompson
171cf7413b Replaced LOGWPL with LOGBWPL (Bus words per line) and LOGCWPL (cache words per line). Replaced with wordlen/8 bytemask. 2022-08-01 21:08:14 -05:00
Ross Thompson
5d9dab6149 pulled swbbytemask out of subword write. 2022-08-01 20:48:45 -05:00
Ross Thompson
5cd6c8069d signal name cleanup. 2022-07-22 23:36:27 -05:00
Katherine Parry
452b017f9a found the bug in the store modification 2022-07-12 22:42:19 +00:00
Katherine Parry
ca4fe08fd9 renamed FLoad2 to FStore2 2022-07-09 00:26:45 +00:00
Katherine Parry
cd53ae67d9 moved fpu ieu write data mux to lsu 2022-07-08 23:56:57 +00:00
David Harris
d73645944f APB CLINT passing regression 2022-07-05 15:51:35 +00:00
Katherine Parry
6baded9121 added rv32 double precision stores - untested 2022-06-28 21:33:31 +00:00
Katherine Parry
254ebf478e added fld in rv32 - needs testing 2022-06-20 22:53:13 +00:00
slmnemo
054cf5f7b0 Reworked AHB fsm to support one cycle latency read and writes, renamed key signals to better reflect their use, and fixed HTRANS errors 2022-06-08 15:03:15 -07:00
slmnemo
284e0395a0 Merge branch 'main' into cacheburstmode 2022-06-08 02:21:33 +00:00
slmnemo
2d76953d42 Added lock signal to ensure AHB speaks with the right bus 2022-06-08 02:19:21 +00:00
slmnemo
73e0c1c07f Reworked bus to handle burst interfacing 2022-06-07 11:22:53 +00:00