forked from Github_Repos/cvw
352 lines
17 KiB
Systemverilog
352 lines
17 KiB
Systemverilog
///////////////////////////////////////////
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// lsu.sv
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//
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// Written: David_Harris@hmc.edu 9 January 2021
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// Modified:
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//
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// Purpose: Load/Store Unit
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// Top level of the memory-stage core logic
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// Contains data cache, DTLB, subword read/write datapath, interface to external bus
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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// committed means the memory operation in flight cannot be interrupted.
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// cpubusy means the cpu is stalled and the lsu must ensure ReadDataM stalls constant until the stall is removed.
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// chap 5 handling faults to memory by delaying writes to memory stage.
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// chap 6 combing bus with dtim
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// chap 9 complete lsu.
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`include "wally-config.vh"
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module lsu (
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input logic clk, reset,
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input logic StallM, FlushM, StallW, FlushW,
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output logic LSUStallM,
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// connected to cpu (controls)
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input logic [1:0] MemRWM,
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input logic [2:0] Funct3M,
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input logic [6:0] Funct7M,
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input logic [1:0] AtomicM,
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input logic TrapM,
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input logic FlushDCacheM,
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output logic CommittedM,
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output logic SquashSCW,
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output logic DCacheMiss,
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output logic DCacheAccess,
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// address and write data
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input logic [`XLEN-1:0] IEUAdrE,
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(* mark_debug = "true" *)output logic [`XLEN-1:0] IEUAdrM,
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(* mark_debug = "true" *)input logic [`XLEN-1:0] WriteDataM,
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output logic [`LLEN-1:0] ReadDataW,
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// cpu privilege
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input logic [1:0] PrivilegeModeW,
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input logic BigEndianM,
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input logic sfencevmaM,
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// fpu
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input logic [`FLEN-1:0] FWriteDataM,
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input logic FpLoadStoreM,
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// faults
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output logic LoadPageFaultM, StoreAmoPageFaultM,
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output logic LoadMisalignedFaultM, LoadAccessFaultM,
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// cpu hazard unit (trap)
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output logic StoreAmoMisalignedFaultM, StoreAmoAccessFaultM,
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// connect to ahb
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(* mark_debug = "true" *) output logic [`PA_BITS-1:0] LSUHADDR,
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(* mark_debug = "true" *) output logic LSUBusRead,
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(* mark_debug = "true" *) output logic LSUBusWrite,
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(* mark_debug = "true" *) input logic LSUBusAck,
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(* mark_debug = "true" *) input logic LSUBusInit,
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(* mark_debug = "true" *) input logic [`XLEN-1:0] HRDATA,
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(* mark_debug = "true" *) output logic [`XLEN-1:0] LSUHWDATA,
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(* mark_debug = "true" *) input logic LSUHREADY,
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(* mark_debug = "true" *) output logic LSUHWRITE,
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(* mark_debug = "true" *) output logic [2:0] LSUHSIZE,
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(* mark_debug = "true" *) output logic [2:0] LSUHBURST,
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(* mark_debug = "true" *) output logic [1:0] LSUHTRANS,
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(* mark_debug = "true" *) output logic LSUTransComplete,
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// page table walker
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input logic [`XLEN-1:0] SATP_REGW, // from csr
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input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV,
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input logic [1:0] STATUS_MPP,
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input logic [`XLEN-1:0] PCF,
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input logic ITLBMissF,
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input logic InstrDAPageFaultF,
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output logic [`XLEN-1:0] PTE,
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output logic [1:0] PageType,
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output logic ITLBWriteF, SelHPTW,
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input var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0],
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input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0] // *** this one especially has a large note attached to it in pmpchecker.
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);
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logic [`XLEN+1:0] IEUAdrExtM;
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logic [`XLEN+1:0] IEUAdrExtE;
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logic [`PA_BITS-1:0] LSUPAdrM;
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logic DTLBMissM;
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logic DTLBWriteM;
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logic [1:0] NonDTIMMemRWM, PreLSURWM, LSURWM;
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logic [2:0] LSUFunct3M;
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logic [6:0] LSUFunct7M;
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logic [1:0] LSUAtomicM;
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(* mark_debug = "true" *) logic [`XLEN+1:0] PreLSUPAdrM;
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logic [11:0] LSUAdrE;
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logic SelDTIM;
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logic CPUBusy;
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logic DCacheStallM;
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logic CacheableM;
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logic BusStall;
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logic InterlockStall;
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logic IgnoreRequestTLB;
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logic BusCommittedM, DCacheCommittedM;
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logic DataDAPageFaultM;
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logic [`XLEN-1:0] IMWriteDataM, IMAWriteDataM;
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logic [`LLEN-1:0] IMAFWriteDataM;
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logic [`LLEN-1:0] ReadDataM;
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logic [(`LLEN-1)/8:0] ByteMaskM;
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flopenrc #(`XLEN) AddressMReg(clk, reset, FlushM, ~StallM, IEUAdrE, IEUAdrM);
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assign IEUAdrExtM = {2'b00, IEUAdrM};
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assign IEUAdrExtE = {2'b00, IEUAdrE};
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assign LSUStallM = DCacheStallM | InterlockStall | BusStall;
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/////////////////////////////////////////////////////////////////////////////////////////////
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// HPTW and Interlock FSM (only needed if VM supported)
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// MMU include PMP and is needed if any privileged supported
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/////////////////////////////////////////////////////////////////////////////////////////////
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if(`VIRTMEM_SUPPORTED) begin : VIRTMEM_SUPPORTED
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lsuvirtmem lsuvirtmem(.clk, .reset, .StallW, .MemRWM(NonDTIMMemRWM), .AtomicM, .ITLBMissF, .ITLBWriteF,
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.DTLBMissM, .DTLBWriteM, .InstrDAPageFaultF, .DataDAPageFaultM,
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.TrapM, .DCacheStallM, .SATP_REGW, .PCF,
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.STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .PrivilegeModeW,
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.ReadDataM(ReadDataM[`XLEN-1:0]), .WriteDataM, .Funct3M, .LSUFunct3M, .Funct7M, .LSUFunct7M,
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.IEUAdrExtM, .PTE, .IMWriteDataM, .PageType, .PreLSURWM, .LSUAtomicM, .IEUAdrE,
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.LSUAdrE, .PreLSUPAdrM, .CPUBusy, .InterlockStall, .SelHPTW,
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.IgnoreRequestTLB);
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end else begin
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assign {InterlockStall, SelHPTW, PTE, PageType, DTLBWriteM, ITLBWriteF, IgnoreRequestTLB} = '0;
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assign CPUBusy = StallW; assign PreLSURWM = NonDTIMMemRWM;
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assign LSUAdrE = IEUAdrE[11:0];
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assign PreLSUPAdrM = IEUAdrExtM;
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assign LSUFunct3M = Funct3M; assign LSUFunct7M = Funct7M; assign LSUAtomicM = AtomicM;
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assign IMWriteDataM = WriteDataM;
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end
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// CommittedM tells the CPU's privilege unit the current instruction
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// in the memory stage is a memory operaton and that memory operation is either completed
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// or is partially executed. Partially completed memory operations need to prevent an interrupts.
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// There is not a clean way to restore back to a partial executed instruction. CommiteedM will
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// delay the interrupt until the LSU is in a clean state.
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assign CommittedM = SelHPTW | DCacheCommittedM | BusCommittedM;
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// MMU and Misalignment fault logic required if privileged unit exists
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// *** DH: This is too strong a requirement. Separate MMU in `VIRTMEM_SUPPORTED from simpler faults in `ZICSR_SUPPORTED
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if(`ZICSR_SUPPORTED == 1) begin : dmmu
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logic DisableTranslation;
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assign DisableTranslation = SelHPTW | FlushDCacheM;
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mmu #(.TLB_ENTRIES(`DTLB_ENTRIES), .IMMU(0))
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dmmu(.clk, .reset, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP,
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.PrivilegeModeW, .DisableTranslation,
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.VAdr(PreLSUPAdrM),
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.Size(LSUFunct3M[1:0]),
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.PTE,
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.PageTypeWriteVal(PageType),
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.TLBWrite(DTLBWriteM),
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.TLBFlush(sfencevmaM),
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.PhysicalAddress(LSUPAdrM),
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.TLBMiss(DTLBMissM),
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.Cacheable(CacheableM), .Idempotent(), .AtomicAllowed(),
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.InstrAccessFaultF(), .LoadAccessFaultM, .StoreAmoAccessFaultM,
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.InstrPageFaultF(),.LoadPageFaultM, .StoreAmoPageFaultM,
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.LoadMisalignedFaultM, .StoreAmoMisalignedFaultM, // *** these faults need to be supressed during hptw.
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.DAPageFault(DataDAPageFaultM),
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// *** should use LSURWM as this is includes the lr/sc squash. However this introduces a combo loop
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// from squash, depends on LSUPAdrM, depends on TLBHit, depends on these *AccessM inputs.
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.AtomicAccessM(|LSUAtomicM), .ExecuteAccessF(1'b0),
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.WriteAccessM(PreLSURWM[0]), .ReadAccessM(PreLSURWM[1]),
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.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW);
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end else begin
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// Determine which region of physical memory (if any) is being accessed
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// conditionally move adredecs to here and ifu.
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// the lsu will output LSUHSel to EBU (need the same for ifu).
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// The ebu will have a mux to select between LSUHSel, IFUHSel
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// mux for HWSTRB
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// adrdecs out of uncore.
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assign {DTLBMissM, LoadAccessFaultM, StoreAmoAccessFaultM, LoadMisalignedFaultM, StoreAmoMisalignedFaultM} = '0;
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assign {LoadPageFaultM, StoreAmoPageFaultM} = '0;
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assign LSUPAdrM = PreLSUPAdrM;
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assign CacheableM = '1;
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end
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/////////////////////////////////////////////////////////////////////////////////////////////
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// Memory System
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// Either Data Cache or Data Tightly Integrated Memory or just bus interface
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/////////////////////////////////////////////////////////////////////////////////////////////
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logic [`LLEN-1:0] LSUWriteDataM, LittleEndianWriteDataM;
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logic [`LLEN-1:0] ReadDataWordM, LittleEndianReadDataWordM;
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logic [`LLEN-1:0] ReadDataWordMuxM;
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logic IgnoreRequest;
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assign IgnoreRequest = IgnoreRequestTLB | TrapM;
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if (`DTIM_SUPPORTED) begin : dtim
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logic [`PA_BITS-1:0] DTIMAdr;
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logic DTIMAccessRW;
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logic MemStage;
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// The DTIM uses untranslated addresses, so it is not compatible with virtual memory.
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// Don't perform size checking on DTIM
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/* verilator lint_off WIDTH */
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assign MemStage = CPUBusy | MemRWM[0] | reset; // 1 = M stage; 0 = E stage
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assign DTIMAdr = MemStage ? IEUAdrExtM : IEUAdrExtE; // zero extend or contract to PA_BITS
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/* verilator lint_on WIDTH */
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assign DTIMAccessRW = |MemRWM;
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adrdec dtimdec(IEUAdrExtM, `DTIM_BASE, `DTIM_RANGE, `DTIM_SUPPORTED, DTIMAccessRW, 2'b10, 4'b1111, SelDTIM); // maybe we pull this out of the mmu?
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//assign NonDTIMMemRWM = MemRWM & ~{2{SelDTIM}}; // disable access to bus-based memory map when DTIM is selected
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assign NonDTIMMemRWM = MemRWM; // *** fix
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dtim dtim(.clk, .reset, .MemRWM,
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.Adr(DTIMAdr),
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.TrapM, .WriteDataM(LSUWriteDataM),
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.ReadDataWordM(ReadDataWordM[`XLEN-1:0]), .ByteMaskM(ByteMaskM[`XLEN/8-1:0]));
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end else begin
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assign SelDTIM = 0; assign NonDTIMMemRWM = MemRWM;
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end
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if (`BUS) begin : bus
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localparam integer WORDSPERLINE = `DCACHE ? `DCACHE_LINELENINBITS/`XLEN : 1;
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localparam integer LOGBWPL = `DCACHE ? $clog2(WORDSPERLINE) : 1;
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if(`DCACHE) begin : dcache
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localparam integer LINELEN = `DCACHE ? `DCACHE_LINELENINBITS : `XLEN;
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logic [LINELEN-1:0] FetchBuffer;
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logic [`PA_BITS-1:0] DCacheBusAdr;
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logic DCacheWriteLine;
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logic DCacheFetchLine;
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logic [LOGBWPL-1:0] WordCount;
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logic SelUncachedAdr, DCacheBusAck;
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logic SelBusWord;
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cache #(.LINELEN(`DCACHE_LINELENINBITS), .NUMLINES(`DCACHE_WAYSIZEINBYTES*8/LINELEN),
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.NUMWAYS(`DCACHE_NUMWAYS), .LOGBWPL(LOGBWPL), .WORDLEN(`LLEN), .MUXINTERVAL(`XLEN), .DCACHE(1)) dcache(
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.clk, .reset, .CPUBusy, .SelBusWord, .RW(LSURWM), .Atomic(LSUAtomicM),
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.FlushCache(FlushDCacheM), .NextAdr(LSUAdrE), .PAdr(LSUPAdrM),
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.ByteMask(ByteMaskM), .WordCount,
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.FinalWriteData(LSUWriteDataM), .Cacheable(CacheableM),
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.CacheStall(DCacheStallM), .CacheMiss(DCacheMiss), .CacheAccess(DCacheAccess),
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.IgnoreRequestTLB, .TrapM, .CacheCommitted(DCacheCommittedM),
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.CacheBusAdr(DCacheBusAdr), .ReadDataWord(ReadDataWordM),
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.FetchBuffer, .CacheFetchLine(DCacheFetchLine),
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.CacheWriteLine(DCacheWriteLine), .CacheBusAck(DCacheBusAck), .InvalidateCache(1'b0));
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cachedp #(WORDSPERLINE, LINELEN, LOGBWPL, `DCACHE) cachedp(
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.clk, .reset,
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.HRDATA, .BusAck(LSUBusAck), .BusInit(LSUBusInit), .BusWrite(LSUBusWrite),
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.BusRead(LSUBusRead), .HSIZE(LSUHSIZE), .HBURST(LSUHBURST), .HTRANS(LSUHTRANS), .BusTransComplete(LSUTransComplete),
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.WordCount, .SelBusWord,
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.Funct3(LSUFunct3M), .HADDR(LSUHADDR), .CacheBusAdr(DCacheBusAdr), .CacheFetchLine(DCacheFetchLine),
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.CacheWriteLine(DCacheWriteLine), .CacheBusAck(DCacheBusAck), .FetchBuffer, .PAdr(LSUPAdrM),
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.SelUncachedAdr, .IgnoreRequest, .RW(LSURWM), .CPUBusy, .Cacheable(CacheableM),
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.BusStall, .BusCommitted(BusCommittedM));
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mux2 #(`LLEN) UnCachedDataMux(.d0(LittleEndianReadDataWordM), .d1({{`LLEN-`XLEN{1'b0}}, FetchBuffer[`XLEN-1:0]}),
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.s(SelUncachedAdr), .y(ReadDataWordMuxM));
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mux2 #(`XLEN) LSUHWDATAMux(.d0(ReadDataWordM[`XLEN-1:0]), .d1(LSUWriteDataM[`XLEN-1:0]),
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.s(SelUncachedAdr), .y(LSUHWDATA));
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end else begin : passthrough // just needs a register to hold the value from the bus
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assign LSUHADDR = LSUPAdrM;
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assign LSUHSIZE = LSUFunct3M;
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flopen #(`XLEN) fb(.clk, .en(LSUBusRead), .d(HRDATA), .q(ReadDataWordM));
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assign LSUHWDATA = LSUWriteDataM[`XLEN-1:0];
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/* -----\/----- EXCLUDED -----\/-----
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busfsm #(LOGBWPL) busfsm(
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.clk, .reset, .RW(LSURWM & ~{IgnoreRequest, IgnoreRequest}),
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.BusAck(LSUBusAck), .BusInit(LSUBusInit), .CPUBusy,
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.BusStall, .BusWrite(LSUBusWrite), .BusRead(LSUBusRead),
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.HTRANS(LSUHTRANS), .BusCommitted(BusCommittedM));
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-----/\----- EXCLUDED -----/\----- */
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AHBBusfsm busfsm(.HCLK(clk), .HRESETn(~reset), .RW(LSURWM & ~{IgnoreRequest, IgnoreRequest}),
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.BusCommitted(BusCommittedM), .CPUBusy, .BusStall, .HREADY(LSUHREADY), .HTRANS(LSUHTRANS),
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.HWRITE(LSUHWRITE));
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assign ReadDataWordMuxM = LittleEndianReadDataWordM; // from byte swapping
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assign LSUHBURST = 3'b0;
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assign LSUTransComplete = LSUBusAck;
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assign {DCacheStallM, DCacheCommittedM, DCacheMiss, DCacheAccess} = '0;
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end
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end else begin: nobus // block: bus
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assign LSUHWDATA = '0;
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assign ReadDataWordMuxM = LittleEndianReadDataWordM;
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assign {BusStall, BusCommittedM} = '0;
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assign {DCacheMiss, DCacheAccess} = '0;
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assign {DCacheStallM, DCacheCommittedM} = '0;
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end
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/////////////////////////////////////////////////////////////////////////////////////////////
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// Atomic operations
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/////////////////////////////////////////////////////////////////////////////////////////////
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if (`A_SUPPORTED) begin:atomic
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atomic atomic(.clk, .reset, .StallW, .ReadDataM(ReadDataM[`XLEN-1:0]), .IMWriteDataM, .LSUPAdrM,
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.LSUFunct7M, .LSUFunct3M, .LSUAtomicM, .PreLSURWM, .IgnoreRequest,
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.IMAWriteDataM, .SquashSCW, .LSURWM);
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end else begin:lrsc
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assign SquashSCW = 0; assign LSURWM = PreLSURWM; assign IMAWriteDataM = IMWriteDataM;
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end
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if (`F_SUPPORTED)
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mux2 #(`LLEN) datamux({{{`LLEN-`XLEN}{1'b0}}, IMAWriteDataM}, FWriteDataM, FpLoadStoreM, IMAFWriteDataM);
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else assign IMAFWriteDataM = IMAWriteDataM;
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/////////////////////////////////////////////////////////////////////////////////////////////
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// Subword Accesses
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/////////////////////////////////////////////////////////////////////////////////////////////
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subwordread subwordread(.ReadDataWordMuxM, .LSUPAdrM(LSUPAdrM[2:0]),
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.FpLoadStoreM, .Funct3M(LSUFunct3M), .ReadDataM);
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subwordwrite subwordwrite(.LSUPAdrM(LSUPAdrM[2:0]),
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.LSUFunct3M, .IMAFWriteDataM, .LittleEndianWriteDataM);
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// Compute byte masks
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swbytemask #(`LLEN) swbytemask(.Size(LSUFunct3M), .Adr(LSUPAdrM[$clog2(`LLEN/8)-1:0]), .ByteMask(ByteMaskM));
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/////////////////////////////////////////////////////////////////////////////////////////////
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// MW Pipeline Register
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/////////////////////////////////////////////////////////////////////////////////////////////
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flopen #(`LLEN) ReadDataMWReg(clk, ~StallW, ReadDataM, ReadDataW);
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/////////////////////////////////////////////////////////////////////////////////////////////
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// Big Endian Byte Swapper
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// hart works little-endian internally
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// swap the bytes when read from big-endian memory
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/////////////////////////////////////////////////////////////////////////////////////////////
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if (`BIGENDIAN_SUPPORTED) begin:endian
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bigendianswap #(`LLEN) storeswap(.BigEndianM, .a(LittleEndianWriteDataM), .y(LSUWriteDataM));
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bigendianswap #(`LLEN) loadswap(.BigEndianM, .a(ReadDataWordM), .y(LittleEndianReadDataWordM));
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end else begin
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assign LSUWriteDataM = LittleEndianWriteDataM;
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assign LittleEndianReadDataWordM = ReadDataWordM;
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end
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endmodule
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