Ross Thompson
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b52f593ecb
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Reorganized the configs.
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2022-10-09 16:46:48 -05:00 |
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David Harris
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6092ca757a
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New fdivsqrtqsel4cmp module based on comparators rather than table lookup
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2022-10-09 04:47:44 -07:00 |
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David Harris
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dceb6f9034
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Moved shift into divsqrt stage and cleaned up comments
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2022-10-09 04:45:45 -07:00 |
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David Harris
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55e4911cf0
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fdivsqrt code cleanup
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2022-10-09 03:37:27 -07:00 |
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Ross Thompson
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382ccf74a5
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Cleaned up the new muxes to select between IROM/ICACHE/BUS and DTIM/DCACHE/BUS.
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2022-10-05 15:46:53 -05:00 |
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Ross Thompson
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62951ec653
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Fixed wally32e.
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2022-10-05 15:37:01 -05:00 |
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Ross Thompson
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2144343c4a
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Name clarifications.
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2022-10-05 15:36:56 -05:00 |
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Ross Thompson
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2e578eb8d8
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Fixed bug with combined dtim+bus.
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2022-10-05 15:16:01 -05:00 |
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Ross Thompson
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b52ab91028
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Possibly have working dtim + bus config.
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2022-10-05 15:08:20 -05:00 |
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Ross Thompson
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8d01cf32fc
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Updated wavefile.
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2022-10-05 14:55:40 -05:00 |
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Ross Thompson
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a0c5833d6d
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Fixed bug in EBU.
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2022-10-05 14:51:12 -05:00 |
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Ross Thompson
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68aa1434b4
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Modified the LSU and IFU to allow concurrent DTIM/DCACHE+BUS and IROM/ICACHE+BUS.
Don't use this commit as the rv32i tests are not passing.
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2022-10-05 14:51:02 -05:00 |
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Ross Thompson
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20546857e6
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-10-05 14:03:44 -05:00 |
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David Harris
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f318daa605
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Changed RV32i config to use DTIM and bus. Don't use this commit - it will break rv32i tests.
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2022-10-05 11:46:52 -07:00 |
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Ross Thompson
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e6b36d0c02
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Optimized the ebu's beat counting.
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2022-10-05 10:58:23 -05:00 |
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Ross Thompson
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3f59ea6b6d
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-10-04 17:38:49 -05:00 |
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Ross Thompson
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92d7be645b
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Reordered the eviction and fetch in cache so it follows a more logical order.
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2022-10-04 17:36:07 -05:00 |
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Ross Thompson
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52e8e0f5ef
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Modified cache lru to not have the delayed write.
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2022-10-04 15:14:58 -05:00 |
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Kip Macsai-Goren
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d5cd67cf09
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fixed endianness mstatush problem, passes make, not regression
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2022-10-04 17:37:39 +00:00 |
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Kip Macsai-Goren
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2bbcec680f
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addded renamed file
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2022-10-04 17:37:05 +00:00 |
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Kip Macsai-Goren
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c4441eb0fa
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally
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2022-10-04 17:33:54 +00:00 |
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Kip Macsai-Goren
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175e824a61
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Renamed endianswap to match module name
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2022-10-04 17:33:49 +00:00 |
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Ross Thompson
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56cc04316c
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Fixed a very subtle bug in the trap handler. It was possible to select the wrong cause if an interrupt was pending, but it was supressed by Committed and another exception triggered.
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2022-10-02 16:21:21 -05:00 |
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Ross Thompson
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02ed8fc301
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-10-01 15:01:22 -05:00 |
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Ross Thompson
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bc94f4aef1
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Disable IFU bus access on TrapM.
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2022-10-01 14:54:16 -05:00 |
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Ross Thompson
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e6db1c5cf8
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Added logic to not implement the save/restore muxes for LSU in the EBU's controller input stage.
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2022-09-29 18:37:34 -05:00 |
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David Harris
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fc4146f409
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Adding start signals for integer divider to fdivsqrt
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2022-09-29 16:30:25 -07:00 |
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Ross Thompson
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47e936cab3
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Renamed signals in EBU.
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2022-09-29 18:29:38 -05:00 |
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cturek
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c72e2e5d49
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Added integer inputs and flags to divsqrt
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2022-09-29 23:08:27 +00:00 |
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Ross Thompson
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f9c4b32bd5
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Simplification to EBU.
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2022-09-29 18:06:34 -05:00 |
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Ross Thompson
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146ff6ff6a
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Fixed HTRANS not changing after accepting HREADY. This exposed a bug in uncore.
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2022-09-29 11:54:03 -05:00 |
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Ross Thompson
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638e506d0b
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Hmm. the icache and ifu didn't have a CommittedF signals going back to the privileged unit. They probably should. If an interrupt occurred during the middle of an instruction fetch icache miss I think it would corrupt the icache.
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2022-09-28 17:39:51 -05:00 |
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Ross Thompson
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87485ed237
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Possible fix for ifu/lsu arbiration issue.
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2022-09-27 17:24:35 -05:00 |
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Ross Thompson
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afc6934249
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Possible fix to the bus cache interaction.
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2022-09-27 11:34:33 -05:00 |
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Ross Thompson
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dfe6bdd06d
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Found a hidden bug in the cache to bus fsm interlock.
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2022-09-26 17:41:30 -05:00 |
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Ross Thompson
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f24b0feeed
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renamed ahbmulticontroller to ebu.
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2022-09-26 14:37:18 -05:00 |
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Ross Thompson
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fd47cf05c3
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-09-26 12:49:16 -05:00 |
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Ross Thompson
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fd2a8e621a
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Yesterday David and I found what is likely a bug in our AHB implementation. HTRANS was getting reset to 2 rather than 0 at the end of a burst transaction. This is fixed.
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2022-09-26 12:48:26 -05:00 |
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David Harris
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b5d2bbe7ca
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changed always_ff to always in sram1p1rw to fix testbench complaint
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2022-09-25 19:56:40 -07:00 |
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Ross Thompson
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dcc00ef4b3
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Renamed RW signals through the caches, bus interfaces, and IFU/LSU.
CPU to $ is called LSURWM or IFURWF.
CPU to Bus is called BusRW
$ to Bus is called CacheBusRW.
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2022-09-23 11:46:53 -05:00 |
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Ross Thompson
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6a6686a34b
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Removed the write first sram model.
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2022-09-22 16:12:08 -05:00 |
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Ross Thompson
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8a6ca027c2
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The valid and dirty bits match the SRAM implementation now.
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2022-09-22 16:09:09 -05:00 |
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Ross Thompson
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29087812e1
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Solved the sram write first / read first issue. Works correctly with read first now.
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2022-09-22 14:16:26 -05:00 |
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Ross Thompson
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f74d21e063
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-09-21 18:24:06 -05:00 |
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Ross Thompson
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cd5b8be78f
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Cleaned up the IFU and LSU around dtim and irom address calculation.
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2022-09-21 18:23:56 -05:00 |
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David Harris
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cfa83fdd98
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For radix 4 division, fixed initial C and then could remove unexplained shift from divshiftcalc
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2022-09-21 13:30:35 -07:00 |
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David Harris
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fce927810a
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Fixed testbench-fp to support all again
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2022-09-21 13:19:48 -07:00 |
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David Harris
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f08d5b23d5
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Eliminated store after store stall when no cache; simplified divshiftcalc logic.
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2022-09-21 13:02:34 -07:00 |
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Ross Thompson
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f83d640068
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Updated IROMAdr logic.
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2022-09-21 12:42:43 -05:00 |
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Ross Thompson
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0294ca0469
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-09-21 12:36:52 -05:00 |
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Ross Thompson
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cdc80c1f28
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Moved other SRAMs to generic/mem.
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2022-09-21 12:36:03 -05:00 |
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David Harris
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3b0714b059
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-09-21 10:35:11 -07:00 |
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David Harris
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1c8581dd6d
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Simplified shipping in divshiftcalc; enhanced testbench-fp to be able to run all 32-bit tests generated by sqrttest
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2022-09-21 10:35:08 -07:00 |
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Ross Thompson
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427db1f55f
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Renamed brom1p1r to rom1p1r.
removed used file bram2p1r1w.sv.
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2022-09-21 12:31:20 -05:00 |
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Ross Thompson
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234cf7510e
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-09-21 12:20:12 -05:00 |
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Ross Thompson
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91fcca9d17
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Merged together bram1p1rw with sram1p1rw as sram1p1rw.
Fixed a major issue with the real SRAM implemenation.
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2022-09-21 12:20:00 -05:00 |
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Ross Thompson
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d6fa8d51d7
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Modified sram1p1rw to support 3 different implementation styles.
SRAM, Read first, and Write first.
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2022-09-21 11:26:00 -05:00 |
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David Harris
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f87e15388a
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commented SpecialCase
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2022-09-21 05:02:08 -07:00 |
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David Harris
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b21e36a788
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Added SpecialCaseReg to hold SpecialCase for fdivsqrtpostproc
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2022-09-21 04:55:43 -07:00 |
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David Harris
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437fd52bf6
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Gated sticky bit in fdiv with SpecialCase
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2022-09-20 20:05:00 -07:00 |
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David Harris
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cf5c513221
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Restored radix 2 to pass regression
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2022-09-20 19:30:16 -07:00 |
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David Harris
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9c8edb9cb6
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renamed u to udigit to avoid conflict with U
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2022-09-20 19:29:23 -07:00 |
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cturek
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e8f2715a81
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Fixed R4 Sqrt overshifting
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2022-09-21 00:05:36 +00:00 |
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cturek
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49a1259cf9
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Fixed fgen4
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2022-09-20 20:00:01 +00:00 |
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Ross Thompson
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c73fae8a96
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Merge branch 'tempMain' into main
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2022-09-20 13:57:38 -05:00 |
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Ross Thompson
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1c2e47e137
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-09-20 11:56:53 -05:00 |
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Ross Thompson
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b2f4d4aaa7
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Added chip enables to sram.
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2022-09-20 10:49:14 -05:00 |
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David Harris
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33af1f97f7
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Define LOGNORMSHIFTSZ
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2022-09-20 08:31:57 -07:00 |
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Ross Thompson
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7470bf7c7c
|
Added comment.
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2022-09-20 09:49:53 -05:00 |
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Ross Thompson
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ea6b687f7c
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-09-20 09:47:16 -05:00 |
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David Harris
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811f498f63
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renamed q to u for unified digit selection
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2022-09-20 04:35:14 -07:00 |
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David Harris
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705a2bd97b
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Removed D2 and D2b from radix2 stage
|
2022-09-20 04:20:38 -07:00 |
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David Harris
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c77ec2aa9c
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Simplified UM initialization
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2022-09-20 04:18:12 -07:00 |
|
David Harris
|
956011b40b
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fdivsqrtfgen4 comments
|
2022-09-20 04:13:21 -07:00 |
|
David Harris
|
8d1408a9d6
|
Moved fpu modules into subdirectories
|
2022-09-20 04:12:05 -07:00 |
|
David Harris
|
0af8151c2a
|
Partitioned fdivsqrt into one module per file and added file names to opening comments
|
2022-09-20 03:57:57 -07:00 |
|
David Harris
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5b13140078
|
Simplified fdivsqrtpostproc QmM logic
|
2022-09-20 03:30:18 -07:00 |
|
David Harris
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8647de5ee4
|
make QmM size b+1 indpenedent of radix
|
2022-09-20 03:25:09 -07:00 |
|
David Harris
|
31c3b62774
|
clean up divshiftcalc
|
2022-09-20 03:19:50 -07:00 |
|
David Harris
|
7177745111
|
clean up divshiftcalc
|
2022-09-20 03:17:29 -07:00 |
|
David Harris
|
b48bbc4294
|
clean up divshiftcalc
|
2022-09-20 03:13:11 -07:00 |
|
David Harris
|
010c88816b
|
clean up divshiftcalc
|
2022-09-20 03:08:25 -07:00 |
|
David Harris
|
712f1d8d3a
|
Cleaning up divshiftcalc LOGNORMSHIFTSZ
|
2022-09-20 02:35:01 -07:00 |
|
Jacob Pease
|
c797aee62c
|
Fixed rxfifotimeout restarting for every new character, even when already high.
|
2022-09-19 18:00:30 -05:00 |
|
cturek
|
85b3e9bfe6
|
Radix 4 sqrt passing first two tests
|
2022-09-19 21:26:32 +00:00 |
|
Ross Thompson
|
6a1b909a3f
|
Fixed up IFU ahb interface names and widths.
|
2022-09-19 10:54:22 -05:00 |
|
David Harris
|
1e6bd26bb6
|
Removed EarlyTermShift from fdiv
|
2022-09-19 08:44:23 -07:00 |
|
David Harris
|
a36747fda0
|
Finished unified divsqrt otfc and fgen name changes
|
2022-09-19 08:30:59 -07:00 |
|
David Harris
|
34bd82e4a3
|
fdivsqrtiter simplification
|
2022-09-19 01:08:01 -07:00 |
|
David Harris
|
b19c37eb0f
|
Reduced number of cycles needed for division
|
2022-09-19 01:02:04 -07:00 |
|
David Harris
|
7826cf0bcb
|
Cleaned up otfc4
|
2022-09-19 00:58:20 -07:00 |
|
David Harris
|
6bab8f0e3f
|
OTFC simplification
|
2022-09-19 00:51:56 -07:00 |
|
David Harris
|
362056f53d
|
Removed unused otfc for Q
|
2022-09-19 00:43:27 -07:00 |
|
David Harris
|
32028c437c
|
fdiv cleanup
|
2022-09-19 00:32:34 -07:00 |
|
David Harris
|
b7b082482f
|
Division working again for radix 2 with unified OTFC
|
2022-09-19 00:30:30 -07:00 |
|
David Harris
|
91194a9c3e
|
Unified on-the-fly conversion working for radix 2; broke radix-4 division
|
2022-09-19 00:04:00 -07:00 |
|
David Harris
|
9fb3382ec3
|
Added 2 bits to C to initialize properly
|
2022-09-18 22:44:22 -07:00 |
|
David Harris
|
33933dd6b0
|
Added 2 bits to C to initialize properly
|
2022-09-18 22:42:35 -07:00 |
|
David Harris
|
24aa410984
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-09-18 21:27:36 -07:00 |
|
David Harris
|
198a134304
|
FP testbench
|
2022-09-18 21:27:21 -07:00 |
|