cvw/pipelined
2022-09-28 17:39:51 -05:00
..
config
misc
regression
src Hmm. the icache and ifu didn't have a CommittedF signals going back to the privileged unit. They probably should. If an interrupt occurred during the middle of an instruction fetch icache miss I think it would corrupt the icache. 2022-09-28 17:39:51 -05:00
testbench