Ross Thompson 638e506d0b Hmm. the icache and ifu didn't have a CommittedF signals going back to the privileged unit. They probably should. If an interrupt occurred during the middle of an instruction fetch icache miss I think it would corrupt the icache.		2022-09-28 17:39:51 -05:00
..
config	Gated sticky bit in fdiv with SpecialCase	2022-09-20 20:05:00 -07:00
misc	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00
regression	Eliminated store after store stall when no cache; simplified divshiftcalc logic.	2022-09-21 13:02:34 -07:00
src	Hmm. the icache and ifu didn't have a CommittedF signals going back to the privileged unit. They probably should. If an interrupt occurred during the middle of an instruction fetch icache miss I think it would corrupt the icache.	2022-09-28 17:39:51 -05:00
testbench	Fixed testbench-fp to support all again	2022-09-21 13:19:48 -07:00