Ross Thompson 382ccf74a5 Cleaned up the new muxes to select between IROM/ICACHE/BUS and DTIM/DCACHE/BUS.		2022-10-05 15:46:53 -05:00
..
config	Changed RV32i config to use DTIM and bus. Don't use this commit - it will break rv32i tests.	2022-10-05 11:46:52 -07:00
misc	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00
regression	Updated wavefile.	2022-10-05 14:55:40 -05:00
src	Cleaned up the new muxes to select between IROM/ICACHE/BUS and DTIM/DCACHE/BUS.	2022-10-05 15:46:53 -05:00
testbench	fixed endianness mstatush problem, passes make, not regression	2022-10-04 17:37:39 +00:00