Ross Thompson 68aa1434b4 Modified the LSU and IFU to allow concurrent DTIM/DCACHE+BUS and IROM/ICACHE+BUS. ... Don't use this commit as the rv32i tests are not passing.		2022-10-05 14:51:02 -05:00
..
config	Changed RV32i config to use DTIM and bus. Don't use this commit - it will break rv32i tests.	2022-10-05 11:46:52 -07:00
misc	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00
regression	Merge branch 'main' of github.com:davidharrishmc/riscv-wally	2022-10-04 17:33:54 +00:00
src	Modified the LSU and IFU to allow concurrent DTIM/DCACHE+BUS and IROM/ICACHE+BUS.	2022-10-05 14:51:02 -05:00
testbench	fixed endianness mstatush problem, passes make, not regression	2022-10-04 17:37:39 +00:00