Github_Repos/cvw
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382 Commits

Author SHA1 Message Date
KelvinTr
01c45ab9d7 Fixed K extension changes 2024-02-28 17:05:08 -06:00
James E. Stine
eb1780a66d control for bitmanip 2024-02-24 22:38:21 -06:00
James E. Stine
ce975a6336 Add ieu main module for k extension 2024-02-24 22:37:04 -06:00
James E. Stine
50cbe54d7b Add datapath.sv 2024-02-24 22:22:19 -06:00
James E. Stine
e06bafe972 Add alu + controller 2024-02-24 22:21:39 -06:00
James E. Stine
cdd2aa6379 tweak of names 2024-02-22 12:27:40 -06:00
James E. Stine
c8468e99c0 slight tweak of names 2024-02-22 12:27:09 -06:00
James E. Stine
550f50debb Modify ALU to handle Zkne/K extension 2024-02-22 11:55:00 -06:00
James E. Stine
7cb170c19b update on aes_instructions 2024-02-21 17:12:50 -06:00
James E. Stine
7097b17785 update aes_instructions 2024-02-21 17:11:34 -06:00
James E. Stine
ac9068d22c update aes_common with style on separate sv 2024-02-21 17:05:58 -06:00
James E. Stine
3d65ea7aba separate aes_shiftword per style file 2024-02-20 22:57:59 -06:00
James E. Stine
f700b7da5a separate galois function SV per the style file 2024-02-20 22:55:34 -06:00
James E. Stine
32be22565a add kmu instruction 2024-02-20 20:18:50 -06:00
James E. Stine
38348f9784 Add SHA instructions 2024-02-20 20:01:12 -06:00
James E. Stine
2cf1d43ec5 add aes instructions 2024-02-20 19:39:26 -06:00
James E. Stine
93d9bb4bc4 minor changes + date change on copyright 2024-02-20 19:13:11 -06:00
James E. Stine
488583aed9 minor tweak 2024-02-20 18:42:34 -06:00
James E. Stine
0cc0cdeae2 initial seed of AES engine 2024-02-20 18:31:17 -06:00
Rose Thompson
aa15a63d9c Merge branch 'main' of https://github.com/openhwgroup/cvw 2024-01-31 13:12:32 -06:00
David Harris
45e2317636 Added Wally github address to header comments 2024-01-29 05:38:11 -08:00
Rose Thompson
4c2ba2b0b4 Added StoreStall back to csrc. 2024-01-18 14:43:34 -06:00
Rose Thompson
83df3dfe83 Fixed the zifencei bug (part of issue 405). 2024-01-15 16:02:37 -06:00
David Harris
d7b016e8f3 Cleaned up Zicond implementation 2024-01-12 18:12:52 -08:00
David Harris
9eb6d9c8b8 Added Zicond support 2024-01-11 07:37:15 -08:00
Rose Thompson
626b89320c More cleanup. 2023-12-29 16:51:39 -06:00
Rose Thompson
0264a17f77 Reverted dtim to use store delay stall, but only (load after store). 2023-12-29 16:06:30 -06:00
Rose Thompson
fbab9f6c6d Updated comments about AMO and CMO stalls. 2023-12-29 15:31:11 -06:00
David Harris
2c2f692f3a Moved forwarding logic into controller 2023-12-26 21:17:01 -08:00
David Harris
6cb4a9e905 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-12-15 19:27:10 -08:00
Rose Thompson
438451ee02 Fixed the AMO hazard. 2023-12-15 11:55:54 -06:00
David Harris
51b43bffa3 ALU cleanup 2023-12-14 19:06:39 -08:00
Rose Thompson
1ca9a8be6d I think I solved the AMO/store hazard issue introduced by removing the store delay hazard. 2023-12-14 16:31:02 -06:00
Rose Thompson
a7f0aaa722 Added comments to finish store delay stall removal. 2023-12-13 20:35:13 -06:00
Rose Thompson
f3d43a7713 Progress on reducing store stall in d cache. 2023-12-13 15:34:21 -06:00
Rose Thompson
13bb5d845b On the way to solving the store delay hazard. 2023-12-13 10:39:01 -06:00
Rose Thompson
80336493f5 Cleaned up redundant ZICBOM/Z_SUPPORTED. 2023-11-29 15:20:49 -06:00
Rose Thompson
69653e5faa Fixed minor bug in the cbo hazard logic. 2023-11-27 23:38:53 -06:00
David Harris
d3ce683e06 Removed other unused signals from Verilog 2023-11-20 23:37:56 -08:00
David Harris
acc2db256f turn off IDIVONFPU when FSUPPORTED=0. Already checked in sim, but need it in synth too for feature sweep 2023-11-17 20:25:24 -08:00
David Harris
434d6b2c5c minfo test working again with mconfigptr for RV64 2023-10-15 06:41:52 -07:00
David Harris
e75ceb044f Improved tlb and controller coverage; fixed exclusions on broken lines 2023-08-31 00:27:47 -07:00
David Harris
f7b50f4721 Preparing to merge with CBO* changes 2023-08-25 18:41:03 -07:00
Ross Thompson
21129dde71 Fixed cbo instruction decode. 2023-08-18 11:32:30 -05:00
Ross Thompson
9dcc70d6c1 Updated the hazard logic for CMO operations. 2023-08-17 17:58:49 -05:00
Ross Thompson
12beada55b Fixed the privilege decoder bug which prevented the fpga linux boot. 2023-07-10 17:00:06 -05:00
David Harris
afe66d0ee4 Added prefetch instructions; sent cbo instructions to LSU 2023-07-02 10:55:35 -07:00
David Harris
723b8266cb Added prefetch signals 2023-07-02 10:06:58 -07:00
David Harris
482e4e6e92 Enhanced decoder to produce individual CMOpE output for the 4 CMO instructions 2023-07-02 09:35:05 -07:00
David Harris
b6ae5661b4 Added environment configuration control (menvcfg/senvcfg) of cbo instructions 2023-07-02 01:52:25 -07:00
David Harris
15314a9c9a Gated floating-point load/stores with STATUS_FS and added initial decoding for Cache Management Operations 2023-07-02 00:34:30 -07:00
David Harris
41e9f20943 improved decoder checking atomic and RW and MW and privileged instructions 2023-07-02 00:02:03 -07:00
David Harris
e34ef4d636 improved decoder checking atomic instructions 2023-07-01 23:10:57 -07:00
David Harris
d930be332e Improved instruction decoding for illegal floating-point loads/stores and fences 2023-07-01 22:48:04 -07:00
David Harris
c383407d5c Removed redundant and not-covered atomic check from StoreStallD 2023-06-16 16:05:53 -07:00
Ross Thompson
4428babda9 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-06-15 15:38:38 -05:00
Ross Thompson
85567841eb Merge branch 'testbench-params2' 2023-06-15 15:31:13 -05:00
David Harris
9e839988dc Gated MDU to save power; doesn't seem to have affected simulation time 2023-06-15 12:17:23 -07:00
David Harris
9f88848832 Bit manipulation comment cleanup 2023-06-15 12:16:46 -07:00
Ross Thompson
75b5c23edd Actually removed old `define configuration file for rv64gc. There were a lot of dangling problems. 2023-06-15 14:05:44 -05:00
David Harris
a62211bad1 Gated inputs to BMU when inactive to save power and simulation time 2023-06-15 11:56:59 -07:00
Ross Thompson
b8a243827b Found a whole bunch of files still using the old `define configurations. 2023-06-15 13:09:07 -05:00
Ross Thompson
60e87b08c4 Improved simulation speed by gating bitmanip zbc's clmul's X and Y inputs with BSelect != 11. Reduced simulation time from 3m45s to 2m35s. 2023-06-14 15:28:58 -05:00
Harshini Srinath
5f73c9727f Update shifter.sv 
Program clean up
 2023-06-12 12:23:45 -07:00
Harshini Srinath
0f36cbd830 Update regfile.sv 
Program clean up
 2023-06-12 12:21:25 -07:00
Harshini Srinath
f1cef043c6 Update ieu.sv 
Program clean up
 2023-06-12 12:19:04 -07:00
Harshini Srinath
304adcb9b0 Update extend.sv 
Program clean up
 2023-06-12 12:15:33 -07:00
Harshini Srinath
1d24a9c912 Update datapath.sv 
Program clean up
 2023-06-12 12:13:58 -07:00
Ross Thompson
052bc95966 More parameterization. Copied Lim. Still no slow down. 2023-05-24 14:49:22 -05:00
Ross Thompson
b91b54589e Updated a large number of the source files to use parameters rather than `defines. Based on Lim's work. So far there is no simulation slow down. 2023-05-24 14:05:44 -05:00
David Harris
a929656d9a Renamed byteUnit to byteop 2023-04-27 14:10:46 -07:00
Limnanthes Serafini
b3976daccd More cleanup 2023-04-13 21:34:50 -07:00
Limnanthes Serafini
034c289a36 Misc typo and indent fixing. 2023-04-13 16:54:15 -07:00
Ross Thompson
52d1c19509 Merge pull request #194 from davidharrishmc/dev 
Bit manipulation support in ImperasDV.  Test improvements.
 2023-04-04 09:13:27 -05:00
Kevin Kim
acebdeeb81 reduced mux3 to mux2 for input signal to clmul 2023-04-03 22:53:46 -07:00
David Harris
4e2d80476e Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-04-03 06:13:16 -07:00
Kevin Kim
8252706691 removed comparator flag to ALU 2023-04-02 21:14:31 -07:00
Kevin Kim
238e97d379 signal renaming on bitmanip alu and alu 2023-04-02 18:42:41 -07:00
Kevin Kim
f175f7e927 changed signal names on clmul and zbc to match book 2023-04-02 18:28:09 -07:00
David Harris
db542543cb Coverage improvement: ieu, hazard, priv 2023-03-31 08:34:34 -07:00
David Harris
fd0c9e973d Coverage improvements in ieu, hazard units 2023-03-31 08:33:46 -07:00
Kevin Kim
2c6359b097 only pass in relevant comparator flag to ALU 2023-03-30 19:15:33 -07:00
Kevin Kim
1e88ec7eac Merge branch 'bitmanip_cleanup' of https://github.com/kipmacsaigoren/cvw into bitmanip_cleanup 2023-03-30 19:04:41 -07:00
Kevin Kim
27a5c9c5d6 Merge branch 'openhwgroup:main' into bitmanip_cleanup 2023-03-30 19:04:36 -07:00
Alec Vercruysse
46df428e56 add check for legal funct3 for IW instructions 2023-03-28 15:59:48 -07:00
Kevin Kim
582c561cb1 comment formatting 2023-03-28 11:40:19 -07:00
Kevin Kim
926f3d2a5a Merge branch 'openhwgroup:main' into bitmanip_cleanup 2023-03-28 11:31:18 -07:00
Kevin Kim
5d3260de63 removed unnecessary signal indices 2023-03-26 20:06:55 -07:00
Kevin Kim
f6ce03730a removed unneccesary input signal from zbb 2023-03-26 19:39:49 -07:00
David Harris
0b0d954e7f Merged ross's spacing fixes 2023-03-24 15:47:26 -07:00
David Harris
092d34373f Merge pull request #159 from ross144/main 
Renamed signal to match book
 2023-03-24 15:34:59 -07:00
Ross Thompson
46b1bca4fc Fixed all tap/space issue in RTL. 2023-03-24 17:32:25 -05:00
Kevin Kim
b70ab0fa5a Zero/Sign extend mux in Shifter, Zero extend mux in Bitmanip alu 2023-03-24 11:52:51 -07:00
David Harris
4b9b20bce0 Shifter capitalization 2023-03-24 09:01:07 -07:00
David Harris
89954df49b Query about CondExtA 2023-03-24 08:35:33 -07:00
David Harris
21424d0f86 Shifter sign simplification and capitalization 2023-03-24 08:27:30 -07:00
David Harris
576545e328 ALUControl Elimination 2023-03-24 08:10:48 -07:00
David Harris
f648be8ee2 Merged ALUOp into ALUControl to simplify ALU mux 2023-03-24 07:28:42 -07:00
David Harris
89479391ca Simplified rotate source to shifter 2023-03-24 06:49:26 -07:00
David Harris
e8d6073eca BMU simplifications 2023-03-24 06:18:06 -07:00
David Harris
3bdb176253 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-03-24 05:59:48 -07:00
Kevin Kim
4c73f0fffd minor formatting 2023-03-23 22:28:21 -07:00
Kevin Kim
5a19934511 comments 2023-03-23 22:22:25 -07:00
Kevin Kim
ae162a2694 removed redundant signals 
-fixed some comments too
 2023-03-23 22:20:37 -07:00
Kevin Kim
9c457e3af4 bitmanip alu submodule passes lint and regression 2023-03-23 21:56:03 -07:00
Kevin Kim
443e64bef2 more progress. Failing regression 2023-03-23 20:42:49 -07:00
Kevin Kim
2a2aa0470a Merge branch 'openhwgroup:main' into bitmanip-alu 2023-03-23 19:53:50 -07:00
David Harris
f2864c7305 Merged BMU 2023-03-23 17:24:40 -07:00
Kevin Kim
8e67c64e2c fixed rori rv32 bug 2023-03-23 16:06:46 -07:00
Kevin Kim
51d691215f more progress on bitmanip alu modularization 2023-03-23 16:02:38 -07:00
David Harris
4e1bf6fbe0 Improved IEU and bitmanip test coverage 2023-03-23 14:24:41 -07:00
Kevin Kim
519a0452a5 started bitmanip alu modularization 2023-03-23 14:02:28 -07:00
David Harris
121d1cea62 Added csrwrites.S test case for privileged tests 2023-03-23 10:55:32 -07:00
Kevin Kim
fd00e386b5 remove outdated 2023-03-22 10:34:17 -07:00
Kevin Kim
efa9f09864 updated header comments to indicate chapter 15 2023-03-22 10:31:21 -07:00
Kevin Kim
f7a915a71a remove helper python script 2023-03-22 10:27:59 -07:00
Kevin Kim
fce62fc213 formatting 2023-03-22 10:26:04 -07:00
Kevin Kim
e9f90050d5 min/max mux optimize 2023-03-22 10:25:54 -07:00
Kevin Kim
c8a5514ca5 formatting 2023-03-22 10:14:12 -07:00
Kevin Kim
3f46dff23e Merge branch 'main' of https://github.com/openhwgroup/cvw into bit-manip 2023-03-21 11:20:05 -07:00
Kevin Kim
72a8b25272 formatting 2023-03-20 14:25:05 -07:00
Kevin Kim
2ad807728c more structural mux changes 2023-03-20 14:23:54 -07:00
Kevin Kim
4ecfa1bad3 added bitmanip 64 tests to updated regression script 
+ alu structural mux changes
 2023-03-20 14:19:39 -07:00
Kevin Kim
5056eb404c formatting 2023-03-20 13:09:49 -07:00
Kevin Kim
82d52f892b Merge branch 'main' of https://github.com/openhwgroup/cvw into bit-manip 2023-03-20 13:06:10 -07:00
Kevin Kim
b394e343f6 format + min/max structural mux 2023-03-20 09:37:57 -07:00
David Harris
6922298f21 Replaced FenceM with InvalidateICacheM for event counting of fence.i 2023-03-18 09:24:31 -07:00
Kevin Kim
0d0d3b981e more checks in bitmanip decode 2023-03-10 17:17:24 -08:00
Kevin Kim
9b4f3219db formatting 2023-03-10 14:32:01 -08:00
Kevin Kim
c380b0816d removed redundant convinvb signal 2023-03-10 14:18:24 -08:00
Kevin Kim
dcaf9de228 removed redundant condinvb mux 2023-03-10 14:17:38 -08:00
David Harris
33fa7e4706 Simplified SLT and SLTU code in ALU 2023-03-09 15:14:52 -08:00
Kevin Kim
f29e8932a2 more comprehensive illegal b instr. check 2023-03-09 12:44:51 -08:00
Kevin Kim
f335d08bbf fixed bmu bug 
- accidentally deleted count instruction decode
 2023-03-09 12:35:42 -08:00
Kevin Kim
7002221dec cleaner bmu decode logic 2023-03-08 16:22:43 -08:00
Kevin Kim
0ca530fffd Merge branch 'bit-manip' into illegal_specific 2023-03-07 14:07:59 -08:00
Kevin Kim
4bb43892f9 alu formatting 2023-03-07 14:01:47 -08:00
Kevin Kim
26cb1857f3 specifc instruction handling for B's 
- Added BALUSrcBD, BaseALUSrcB for distinguishing between base instruction I/IW and Bitmanip instruction I/IW
 2023-03-07 13:58:08 -08:00
Kip Macsai-Goren
2ec3c741ef Merge branch 'bit-manip' of github.com:kipmacsaigoren/cvw into bit-manip 2023-03-07 13:44:51 -08:00
Kip Macsai-Goren
f178c90c02 Merge branch 'main' of github.com:kipmacsaigoren/cvw into bit-manip 2023-03-07 13:44:19 -08:00
Kevin Kim
bd9b9970f5 Merge remote-tracking branch 'origin' into illegal_specific 2023-03-07 11:30:36 -08:00
Kevin Kim
6d146a7e20 formatting 2023-03-07 10:57:52 -08:00
Kevin Kim
833e7bd2af shifter sign generation logic optimize 2023-03-07 10:57:06 -08:00
Kevin Kim
81198ce6f6 reverted backing to working version 2023-03-07 00:29:58 -08:00
Kevin Kim
5637897dce reverted to working version 2023-03-07 00:28:07 -08:00
David Harris
7ecf4cdea8 Fixed bug about rv64 shifts only using 6 bits of funct7 2023-03-06 13:10:51 -08:00
David Harris
7e0c96cdcc Simplified decoder default to illegal instruction 2023-03-06 11:21:11 -08:00
David Harris
c2efdbdbbb More detailed decoding of load/store/branch/jump 2023-03-06 11:15:48 -08:00
David Harris
a56557d847 Improved decoding illegal instructions in controller 2023-03-06 11:02:42 -08:00
Kevin Kim
c7d1e35d4a structural changes in cnt.sv 2023-03-06 06:44:15 -08:00