Commit Graph

498 Commits

Author SHA1 Message Date
Rose Thompson
92ee56c1a1 Yay. Finally found the bug which prevented wally.do from having functional coverage using riscvISACOV.
testbench.sv was missing the trace2cov instance.
2024-05-27 17:25:20 -05:00
Rose Thompson
4c0261fd2c Closer. Needed to reorder includes and defines. 2024-05-27 15:37:16 -05:00
Rose Thompson
ff611016c7 Closer? 2024-05-27 14:11:02 -05:00
Rose Thompson
2985cfb7eb Preliminary work to merge functional coverage into wally.do. 2024-05-27 11:59:13 -05:00
Rose Thompson
dc09e1c0c5 Modified names so they don't conflict with FPGA's axi signals. 2024-05-24 16:38:47 -05:00
Rose Thompson
1f7d732dca Moved the rvvisynth code to testbench since I only want this for simulation and fpga. 2024-05-24 16:10:58 -05:00
Rose Thompson
bf9f45d319 We have a simulation of the ethernet transmission working.
This commit does not include the source files for the ethernet as it does not belong to cvw.
I'll want to fork that repo and make it a submodule as I need to change the source a bit.
2024-05-24 11:25:42 -05:00
Jordan Carlin
6a2192db6e
Revert "Remove existing derived configs before creating new ones" 2024-05-23 13:56:38 -07:00
Jordan Carlin
fb8e97dd04
Remove existing derived configs before creating new ones 2024-05-23 13:17:24 -07:00
Rose Thompson
b127c19242 Merge branch 'main' into rvvi 2024-05-20 16:31:06 -05:00
Rose Thompson
a885240fbd temporary commit to help debug merging testbench.sv with testbench-imperas.sv 2024-05-17 12:36:00 -05:00
Rose Thompson
bd8450734b Fixed more bugs with wally.do. 2024-05-17 10:39:00 -05:00
Rose Thompson
46e6459965 Updated script to run linux with imperasDV. 2024-05-14 13:46:27 -05:00
Rose Thompson
970af9551c Fixed bug with gui mode testbench_fp
removed old wally-linux-imperas.do
2024-05-14 13:41:20 -05:00
Rose Thompson
30bea18dec Maybe have imperasDV linux simulation merged into wally.do 2024-05-14 12:38:19 -05:00
Rose Thompson
e8f5545076 Got imperasDV running linux simulation again.
Now need to merge do files.
2024-05-13 16:43:13 -05:00
Rose Thompson
ceb31fec68 Merge branch 'main' of https://github.com/openhwgroup/cvw 2024-05-10 08:54:23 -05:00
Rose Thompson
b027fa44ef Merge branch 'main' of https://github.com/openhwgroup/cvw 2024-05-10 08:53:00 -05:00
Rose Thompson
93ea5b0c1e Fixed wavefile to have function logger. 2024-05-10 08:50:42 -05:00
David Harris
04457d49f7 Updated sim-testfloat-verilator to use wsim 2024-05-10 05:03:24 -07:00
David Harris
61e559606e Fixed wsim to be able to invoke TestFloat with Verilator. However, TestFloat produces incorrect results with Verilator 2024-05-09 18:56:59 -07:00
David Harris
0d1d59a3d8 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2024-05-08 18:58:01 -07:00
Divya2030
eff2264752 Code Coverage Text format for each test and configuration in IndividualCovReport 2024-05-08 05:24:24 -07:00
Divya2030
b4b88c5858 VCS regression & Code Coverage 2024-05-08 04:39:42 -07:00
Divya2030
31ae18922b regression_wally vcs run works 2024-05-08 04:25:03 -07:00
David Harris
927f166e1f Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2024-05-07 12:58:40 -07:00
Divya2030
a3f1a274d2 VCS Simulation Passed 2024-05-07 10:41:02 -07:00
David Harris
37fc45cd35 Updated Questa wally.do to terminate on a compile error 2024-05-06 11:28:00 -07:00
Divya2030
48ad4d6001 pmp coverage 2024-05-02 11:52:54 -07:00
Divya2030
3853f94337 Revert "initial commit pmp basic coverage working"
This reverts commit 7ca1c976c0.
2024-05-02 11:23:59 -07:00
Divya2030
7ca1c976c0 initial commit pmp basic coverage working 2024-05-02 10:33:29 -07:00
Kunlin Han
cde284d003 Fix the problem of missing sim/verilator/wkdir 2024-04-30 10:48:42 -07:00
David Harris
8f0c68373e Verilator fulladder example improvmeents 2024-04-28 22:08:00 -07:00
David Harris
1274ec55af Resolved merge conflict 2024-04-26 16:15:23 -07:00
Quswar Abid
f999ccadf4 /cad/mentor/questa_sim-2023.4/questasim is fixed, relative paths to design and testbench files are fixed, and RISCV-DV submodule is updated back to the latest commit on master branch 2024-04-26 15:55:39 -07:00
David Harris
5d97858806 Moved functional coverage files to sim/questa and to tests/riscvdv 2024-04-24 11:46:38 -07:00
David Harris
5f3676dfd7
Merge pull request #753 from quswarabid/riscvdv_bringup
RISCVDV bringup - Coverage Collection on RISCVISACOV
2024-04-24 09:47:34 -07:00
Quswar Abid
7b441d2881 Bringup of RISCV-DV to collect functional coverage - Update to track RV64IMAFDC_Zicsr related coverpoints from riscvISACOV 2024-04-23 18:20:29 -07:00
David Harris
0dc2c7d16a Fixed deriv path in Verilator makefile 2024-04-23 10:19:08 -07:00
David Harris
f9eec8c43f Merged wsim changes 2024-04-22 13:11:35 -07:00
Kunlin Han
9be0303493 Add support for dumping vcd. 2024-04-22 13:03:51 -07:00
David Harris
cc236bdb25 Resolved merge conflicts 2024-04-22 12:16:06 -07:00
Kunlin Han
c134b712c4
Merge branch 'main' into verilator 2024-04-22 11:35:18 -07:00
Kunlin Han
c383bef1ad Run verilator configurations and testsuites in different folders. 2024-04-22 11:32:46 -07:00
David Harris
45196a9959 ignore VCS junk files 2024-04-21 19:49:55 -07:00
David Harris
00a1c0fc57 Fixed WALLY/RISCV paths in testbench/rom1p1r; search log files for warnings and errors 2024-04-21 00:02:15 -07:00
David Harris
fd6a6b2249 environment variable cleanup 2024-04-20 22:52:08 -07:00
David Harris
a1876b1e7c script cleanup 2024-04-20 17:22:31 -07:00
David Harris
571b67f565 Merging PR738 2024-04-20 17:15:17 -07:00
slmnemo
6458fa5642 Merge branch 'main' of https://github.com/openhwgroup/cvw into linux_nightly 2024-04-20 14:46:35 -07:00
David Harris
3cb5cd0cb1 simulator cleanup 2024-04-20 14:12:55 -07:00
David Harris
c8e7a6990d Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2024-04-20 11:44:27 -07:00
David Harris
bf2f6859e4 Changed Verilog makefile to print transcript to stdout by default like Questa; redirected to logfile elsewhere 2024-04-20 11:27:54 -07:00
David Harris
84e8d86d2a
Merge pull request #739 from Karl-Han/deriv_support
Add extra path to search for deriv/buildroot
2024-04-20 11:23:54 -07:00
slmnemo
2b0cf90a99 Merged with merge conflict 2024-04-17 10:47:28 -07:00
Kunlin Han
91a88fa46c Update sim/verilator/Makefile with more comments and merging variables. 2024-04-17 09:52:54 -07:00
Kunlin Han
392eedb342 Update sim/verilator/Makefile with constants for simplicity. 2024-04-16 18:54:11 -07:00
Kunlin Han
6f6b1fd1fd Add extra path to search for deriv/buildroot. 2024-04-16 18:45:21 -07:00
slmnemo
554f818a8c Fixed wave.do to match new conditional generate block names 2024-04-16 14:43:38 -07:00
Rose Thompson
dd3460c1a9 Fixed makefile and regression-wally so that code coverage now works. 2024-04-16 15:44:42 -05:00
Rose Thompson
1eb1beed95 Fixed merge conflict bug in the last pull request. 2024-04-16 10:32:24 -05:00
Rose Thompson
9fe86712d8
Merge branch 'main' into wsim_verilator 2024-04-16 09:07:50 -05:00
David Harris
160162c98a
Merge pull request #728 from Karl-Han/verilator_getenv
Add support for getenvval as wrapper for Verilator's getenv
2024-04-15 17:55:34 -06:00
slmnemo
4b80457f3e Fixed issue with Verilator hierarchical referencing by changing module names, moved run-imperas-linux to correct directory 2024-04-12 21:58:20 -07:00
Kunlin Han
7b5972ea82 Merge branch 'verilator_getenv' into wsim_verilator 2024-04-12 15:27:09 -07:00
Kunlin Han
4d9de94029 Add support for getenvval as wrapper for Verilator's getenv. 2024-04-12 14:59:04 -07:00
Kunlin Han
a55bb01d1d Update README and put logs in the right places. 2024-04-11 20:16:55 -07:00
Kunlin Han
e25177cf4c Add verilator support for wsim. 2024-04-11 20:02:20 -07:00
slmnemo
90040a6a21 Added extra path to run-imperas-linux.sh to match new questa directory with .do files 2024-04-09 16:13:31 -07:00
Rose Thompson
bb072fba84 Fixed the buildroot issue. 2024-04-06 18:25:53 -05:00
Rose Thompson
d0d1166e3f Got the separation of the -G and +variable arguments in the questa do file.
regression still runs.
2024-04-06 18:04:48 -05:00
Rose Thompson
cdcff9d368 Updated sim-wally to work with new run scripts. 2024-04-06 16:32:07 -05:00
Rose Thompson
46fdfde7ec Removed unnecessary display from testbench. 2024-04-06 16:10:18 -05:00
David Harris
c73a48cf22 Removed unused wave-dos 2024-04-06 13:52:13 -07:00
David Harris
e8111da88a Removed unused old regression-wally 2024-04-06 13:47:44 -07:00
David Harris
6b844a2e6e Added GUI support and removed unused wave files 2024-04-06 13:43:06 -07:00
David Harris
3c855e3e90 Passing arguments to buildroot, not yet checking result correctly 2024-04-06 11:42:41 -07:00
David Harris
ac9a21873d Pass TEST to testbench with +TEST=<name> rather than -G TEST=<name> so that we don't have to recompile for every new test 2024-04-06 10:34:21 -07:00
David Harris
347df26713 Fixed regression running; buildroot pending 2024-04-06 09:46:56 -07:00
David Harris
9ee7544d3c TestFloat running; normal testbench broken 2024-04-06 09:28:07 -07:00
David Harris
4b19f6d542 testfloat running through wsim; moved lint, regression, wsim to bin directory so we don't need ./ 2024-04-06 08:22:39 -07:00
David Harris
4cc9dd7583 regression-wally refactoring to support mulitple simulators 2024-04-05 21:45:56 -07:00
David Harris
7b56809323 wsim runs a Questa sim 2024-04-05 19:08:14 -07:00
David Harris
a1d3e5b15e Moved do files into questa 2024-04-05 18:42:48 -07:00
David Harris
a8a03d6011 Reorganizing sim directory for multiple simulators 2024-04-05 18:19:46 -07:00
slmnemo
3ee25c8936 Merged testbench changes 2024-04-05 17:20:03 -07:00
slmnemo
5378b61eb2 Added UART output file buildroot_uart.out for Linux test 'buildroot'. 2024-04-05 17:18:03 -07:00
David Harris
ccd0e9cd0c Clean up testbench-fp for Verilator 2024-04-03 17:26:41 -07:00
David Harris
ae8d581f4e Started implementing Verilator for testfloat 2024-04-03 17:09:19 -07:00
Divya2030
135f3b6f8f vcs testbench 2024-04-03 10:39:02 -07:00
Ross Thompson
101021222b Merge branch 'main' of github.com:ross144/cvw into main 2024-03-29 14:39:39 -05:00
Ross Thompson
33a26fb78c Updates to branch predictor collection. 2024-03-29 13:52:28 -05:00
Quswar Abid
21dd4649de ISACOV is functioning - March 27, 2024 2024-03-26 14:17:41 -07:00
slmnemo
6fbac9ec97 Merge branch 'main' of https://github.com/openhwgroup/cvw into nightly-regression 2024-03-26 10:29:00 -07:00
slmnemo
efb68e7eeb Added dumptvs function to Linux makefile to create linux-testvectors in /opt/riscv directory 2024-03-26 10:28:50 -07:00
David Harris
f0b29d3083 AMO max/min comparator optimization 2024-03-24 17:05:32 -07:00
Kevin Kim
c8b84ebbc5 regression-wally -softfloat with updated derived configs 2024-03-20 09:58:14 -07:00
Kevin Kim
ccf2c270a1 Merge branch 'update_derived_configs' of https://github.com/kevindkim723/cvw into update_derived_configs 2024-03-20 09:54:08 -07:00
Kevin Kim
ac00eaf322 added some missing derived configs 2024-03-20 09:50:52 -07:00
David Harris
c01e4495b1 AES simplification 2024-03-16 07:00:56 -07:00