Merge branch 'main' of https://github.com/openhwgroup/cvw into linux_nightly

sim/verilator/Makefile

@@ -1,15 +1,24 @@
+SHELL := /bin/bash
 .PHONY: profile run questa clean
 
+# verilator configurations
 OPT=
 PARAMS?=-DVERILATOR=1 --no-trace-top
 NONPROF?=--stats
-WORKING_DIR=${WALLY}/sim/verilator
-TARGET=$(WORKING_DIR)/target
-SOURCE=${WALLY}/config/shared/*.vh ${WALLY}/config/${WALLYCONF} ${WALLY}/src/cvw.sv ${WALLY}/testbench/testbench.sv ${WALLY}/testbench/common/*.sv ${WALLY}/src/*/*.sv ${WALLY}/src/*/*/*.sv
-
 WALLYCONF?=rv64gc
 TEST?=arch64i
 
+# constants
+# assume WALLY variable is correctly configured in the shell environment
+WORKING_DIR=${WALLY}/sim/verilator
+TARGET=$(WORKING_DIR)/target
+# INCLUDE_PATH are pathes that Verilator should search for files it needs
+INCLUDE_PATH="-I${WALLY}/config/shared" "-I${WALLY}/config/$(WALLYCONF)" "-I${WALLY}/config/deriv/$(WALLYCONF)"
+# SOURCES are source files
+SOURCES=${WALLY}/src/cvw.sv ${WALLY}/testbench/testbench.sv ${WALLY}/testbench/common/*.sv ${WALLY}/src/*/*.sv ${WALLY}/src/*/*/*.sv
+# DEPENDENCIES are configuration files and source files, which leads to recompilation of executables
+DEPENDENCIES=${WALLY}/config/shared/*.vh $(SOURCES)
+
 default: run
 
 profile: obj_dir_profiling/Vtestbench_$(WALLYCONF)
@@ -26,26 +35,27 @@ run: obj_dir_non_profiling/Vtestbench_$(WALLYCONF)
 	time $(WORKING_DIR)/obj_dir_non_profiling/Vtestbench_$(WALLYCONF) +TEST=$(TEST) 2>&1 > $(WORKING_DIR)/logs/$(WALLYCONF)_$(TEST).log
 	echo "Please check $(WORKING_DIR)/logs/$(WALLYCONF)_$(TEST).log for logs and output files."
 	
-obj_dir_non_profiling/Vtestbench_$(WALLYCONF): $(SOURCE)
+obj_dir_non_profiling/Vtestbench_$(WALLYCONF): $(DEPENDENCIES)
 	mkdir -p obj_dir_non_profiling
 	time verilator \
 	--Mdir obj_dir_non_profiling -o Vtestbench_$(WALLYCONF) \
 	-cc --binary \
 	$(OPT) $(PARAMS) $(NONPROF) \
 	--timescale "1ns/1ns" --timing --top-module testbench  --relative-includes \
-	"-I${WALLY}/config/shared" "-I${WALLY}/config/$(WALLYCONF)" \
+	$(INCLUDE_PATH) \
 	wrapper.c \
-	${WALLY}/src/cvw.sv ${WALLY}/testbench/testbench.sv ${WALLY}/testbench/common/*.sv ${WALLY}/src/*/*.sv ${WALLY}/src/*/*/*.sv
+	$(SOURCES)
 	
-obj_dir_profiling/Vtestbench_$(WALLYCONF): $(SOURCE)
+obj_dir_profiling/Vtestbench_$(WALLYCONF): $(DEPENDENCIES)
 	mkdir -p obj_dir_profiling
 	time verilator \
 	--Mdir obj_dir_profiling -o Vtestbench_$(WALLYCONF) \
 	-cc --binary \
 	--prof-cfuncs $(OPT) $(PARAMS) \
 	--timescale "1ns/1ns" --timing --top-module testbench  --relative-includes \
+	$(INCLUDE_PATH) \
 	wrapper.c \
-	"-I${WALLY}/config/shared" "-I${WALLY}/config/$(WALLYCONF)" ${WALLY}/src/cvw.sv ${WALLY}/testbench/testbench.sv ${WALLY}/testbench/common/*.sv ${WALLY}/src/*/*.sv ${WALLY}/src/*/*/*.sv
+	$(SOURCES)
 
 questa:
 	time vsim -c -do "do ${WALLY}/sim/wally-batch.do $(WALLYCONF) $(TEST)"

src/generic/mem/rom1p1r.sv

@@ -48,7 +48,11 @@ module rom1p1r #(parameter ADDR_WIDTH = 8, DATA_WIDTH = 32, PRELOAD_ENABLED = 0)
 
   initial begin
     if (PRELOAD_ENABLED) begin
+`ifdef VERILATOR
+      $readmemh({getenvval("WALLY"), "/fpga/src/boot.mem"}, ROM, 0);
+`else
       $readmemh("$WALLY/fpga/src/boot.mem", ROM, 0);
+`endif
     end
   end