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Changed Verilog makefile to print transcript to stdout by default like Questa; redirected to logfile elsewhere

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This commit is contained in:
David Harris 2024-04-20 11:27:54 -07:00
parent 7abf98cb4d
commit bf2f6859e4
1 changed files with 3 additions and 2 deletions
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5
sim/verilator/Makefile
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@ -23,8 +23,9 @@ profile: obj_dir_profiling/Vtestbench_$(WALLYCONF)
run: obj_dir_non_profiling/Vtestbench_$(WALLYCONF)
mkdir -p $(WORKING_DIR)/logs
time $(WORKING_DIR)/obj_dir_non_profiling/Vtestbench_$(WALLYCONF) +TEST=$(TEST) 2>&1 > $(WORKING_DIR)/logs/$(WALLYCONF)_$(TEST).log
echo "Please check $(WORKING_DIR)/logs/$(WALLYCONF)_$(TEST).log for logs and output files."
# time $(WORKING_DIR)/obj_dir_non_profiling/Vtestbench_$(WALLYCONF) +TEST=$(TEST) 2>&1 > $(WORKING_DIR)/logs/$(WALLYCONF)_$(TEST).log
time $(WORKING_DIR)/obj_dir_non_profiling/Vtestbench_$(WALLYCONF) +TEST=$(TEST)
# echo "Please check $(WORKING_DIR)/logs/$(WALLYCONF)_$(TEST).log for logs and output files."
obj_dir_non_profiling/Vtestbench_$(WALLYCONF): $(SOURCE)
mkdir -p obj_dir_non_profiling