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Verilator fulladder example improvmeents

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This commit is contained in:
David Harris 2024-04-28 22:08:00 -07:00
parent b50bb4cad8
commit 8f0c68373e
4 changed files with 12 additions and 13 deletions
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1
.gitignore vendored
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@ -188,6 +188,7 @@ sim/cfi/*
sim/branch/*
sim/obj_dir
examples/verilog/fulladder/obj_dir
examples/verilog/fulladder/fulladder.vcd
config/deriv
docs/docker/buildroot-config-src
docs/docker/testvector-generation

3
examples/verilog/fulladder/fulladder.sv
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@ -19,6 +19,8 @@ module testbench();
// at start of test, load vectors and pulse reset
initial
begin
$dumpfile("fulladder.vcd");
$dumpvars;
$readmemb("fulladder.tv", testvectors);
cycle = 0;
vectornum = 0; errors = 0;
@ -47,6 +49,7 @@ module testbench();
$finish;
end
end
endmodule
module fulladder(input logic a, b, c,

6
examples/verilog/fulladder/verilate
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@ -1,5 +1,3 @@
#verilator --timescale "1ns/1ns" --timing -cc --exe --build --top-module testbench fulladder.sv
#verilator --timescale "1ns/1ns" --timing -cc --exe --top-module testbench fulladder.sv
#verilator --binary --top-module testbench fulladder.sv
verilator --timescale "1ns/1ns" --timing --binary --top-module testbench fulladder.sv
verilator --binary --top-module testbench --trace fulladder.sv
obj_dir/Vtestbench

15
sim/verilator/Makefile
View File

@ -30,6 +30,10 @@ DEPENDENCIES=${WALLY}/config/shared/*.vh $(SOURCES)
default: run
run: wkdir/$(WALLYCONF)_$(TEST)/Vtestbench
mkdir -p $(VERILATOR_DIR)/logs
wkdir/$(WALLYCONF)_$(TEST)/Vtestbench +TEST=$(TEST)
profile: obj_dir_profiling/Vtestbench_$(WALLYCONF)
$(VERILATOR_DIR)/obj_dir_profiling/Vtestbench_$(WALLYCONF) +TEST=$(TEST)
mv gmon.out gmon_$(WALLYCONF).out
@ -39,17 +43,13 @@ profile: obj_dir_profiling/Vtestbench_$(WALLYCONF)
mv gmon_$(WALLYCONF)* $(VERILATOR_DIR)/logs_profiling
echo "Please check $(VERILATOR_DIR)/logs_profiling/gmon_$(WALLYCONF)* for logs and output files."
run: wkdir/$(WALLYCONF)_$(TEST)/Vtestbench
mkdir -p $(VERILATOR_DIR)/logs
wkdir/$(WALLYCONF)_$(TEST)/Vtestbench +TEST=$(TEST)
wkdir/$(WALLYCONF)_$(TEST)/Vtestbench: $(DEPENDENCIES)
verilator \
--Mdir wkdir/$(WALLYCONF)_$(TEST) -o Vtestbench \
--binary --trace \
$(OPT) $(PARAMS) $(NONPROF) \
$(EXTRA_ARGS) \
--timescale "1ns/1ns" --timing --top-module testbench --relative-includes \
--top-module testbench --relative-includes \
$(INCLUDE_PATH) \
${WALLY}/sim/verilator/wrapper.c \
$(SOURCES)
@ -61,13 +61,10 @@ obj_dir_profiling/Vtestbench_$(WALLYCONF): $(DEPENDENCIES)
--binary \
--prof-cfuncs $(OPT) $(PARAMS) \
$(EXTRA_ARGS) \
--timescale "1ns/1ns" --timing --top-module testbench --relative-includes \
--top-module testbench --relative-includes \
$(INCLUDE_PATH) \
${WALLY}/sim/verilator/wrapper.c \
$(SOURCES)
questa:
vsim -c -do "do ${WALLY}/sim/wally-batch.do $(WALLYCONF) $(TEST)"
clean:
rm -rf $(VERILATOR_DIR)/wkdir $(VERILATOR_DIR)/obj_dir_profiling $(VERILATOR_DIR)/logs $(VERILATOR_DIR)/logs_profiling