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310 Commits

Author SHA1 Message Date
Ross Thompson
d901cfc848 Merge branch 'icache_bp_bug' into tests 
Not sure this merge is right.
 2021-04-06 21:46:40 -05:00
Ross Thompson
0a20e33971 Steps to getting branch predictor benchmarks running. 2021-04-06 21:20:51 -05:00
Noah Boorstin
c820910b29 add busybear boot files with git-lfs 2021-04-05 19:38:43 -04:00
Noah Boorstin
ce22a1de04 busybear: reenable 'ruthless' CSR checking 2021-04-05 12:53:30 -04:00
bbracker
ce7b2314ef Yee hoo first draft of PLIC plus self-checking tests 2021-04-04 06:40:53 -04:00
Thomas Fleming
8f31e00f6a Merge branch 'mmu' into main 
Conflicts:
	wally-pipelined/src/wally/wallypipelinedhart.sv
 2021-04-03 22:12:52 -04:00
Thomas Fleming
ac89947e98 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-04-03 22:09:50 -04:00
Noah Boorstin
2f503ee6b9 busybear: temporary stop after 800k instrs 2021-04-03 21:37:57 -04:00
Katherine Parry
08b31f7b2a Integrated FPU 2021-04-03 20:52:26 +00:00
James E. Stine
82cd900b65 Put back imperas testbench until figure out why m_supported is running for rv64ic 2021-04-02 08:19:25 -05:00
James E. Stine
9026357350 Added some updates to divider - still not working all the time. Still a bug with signals within muldiv - specificaly MultDivE being modified during Execute stage. Seems to be triggered by ahblite signal. 2021-04-02 06:27:37 -05:00
Thomas Fleming
06032936bd Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-04-01 16:24:06 -04:00
Thomas Fleming
3f3d8f414d Merge branch 'mmu' of github.com:davidharrishmc/riscv-wally into mmu 2021-04-01 16:23:19 -04:00
Thomas Fleming
f9bf2fbc01 Implement sfence.vma and fix tlb writing 2021-04-01 15:55:05 -04:00
Noah Boorstin
4e62c7d5f5 busybear: temporarially stop checking CSRs 2021-03-31 14:14:32 -04:00
Noah Boorstin
679daeedf5 busybear: clean up questa warnings 2021-03-31 14:04:57 -04:00
Noah Boorstin
ddc56d8cd7 busybear: clean up questa warnings 2021-03-31 14:02:15 -04:00
Ross Thompson
1e83810450 Merge of main with the new icache and the branch predictor. I believe there is a bug in the icache with unaligned memory access. The second part of the access is incorrectly relying on the PCF being the address of the next two bytes of the instruction. However this is not always the case as the branch predictor can get the wrong target address. The icache needs to generate the +2 address internally. 2021-03-30 23:18:20 -05:00
Thomas Fleming
e3d548d452 Merge remote-tracking branch 'origin/main' into main 
Bring icache and MMU code together

Conflicts:
	wally-pipelined/src/ifu/ifu.sv
	wally-pipelined/testbench/testbench-imperas.sv
 2021-03-30 22:24:47 -04:00
Thomas Fleming
4b2765f8e2 Complete basic page table walker 2021-03-30 22:19:27 -04:00
Thomas Fleming
7f7cc73dd3 Update virtual memory tests and move to separate folder 2021-03-30 22:18:29 -04:00
Domenico Ottolia
d0a78b15b7 Add one more test to WALLY-CAUSE, and update privileged testgen 2021-03-30 19:44:58 -04:00
Domenico Ottolia
8c7e247b58 Add mcause tests to testbench 2021-03-30 17:17:59 -04:00
ushakya22
ba01d57767 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-30 15:25:07 -04:00
Ross Thompson
a3925505bf fixed some bugs with the RAS. 2021-03-30 13:57:40 -05:00
Jarred Allen
6cda818f09 Merge branch 'cache2' into cache 
Conflicts:
	wally-pipelined/testbench/testbench-imperas.sv
 2021-03-30 13:32:33 -04:00
Jarred Allen
dd0b3fde59 Comment out failing tests 2021-03-30 13:07:26 -04:00
Jarred Allen
335178a1d3 Merge branch 'cache' into main 2021-03-30 12:56:19 -04:00
Jarred Allen
85164c7a87 Merge branch 'main' into cache 
Conflicts:
	wally-pipelined/regression/wave-dos/ahb-waves.do
	wally-pipelined/src/ifu/ifu.sv
	wally-pipelined/testbench/testbench-busybear.sv
	wally-pipelined/testbench/testbench-imperas.sv
 2021-03-30 12:55:01 -04:00
David Harris
9f0a58e193 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-26 13:04:52 -04:00
David Harris
aa0d0d50d8 Added fp test to testbench 2021-03-26 13:03:23 -04:00
Noah Boorstin
606295db2f Merge branch 'main' into cache 
Conflicts:
	wally-pipelined/testbench/testbench-busybear.sv
 2021-03-26 12:26:30 -04:00
Shreya Sanghai
edaf89e3d1 Merge branch 'PPA' into main 
Conflicts:
	wally-pipelined/testbench/testbench-privileged.sv
 2021-03-25 20:35:21 -04:00
Shreya Sanghai
d3e914f64b removed minor bugs 2021-03-25 20:29:50 -04:00
ShreyaSanghai
da4086db79 Removed PCW and InstrW from ifu 2021-03-26 01:53:19 +05:30
Jarred Allen
73d4dd8c15 Begin work on compressed instructions 2021-03-25 14:43:10 -04:00
Noah Boorstin
9eb1786fb1 busybear: quick fix to mem reading 
also stop ignoring mcause at the start
 2021-03-25 14:29:11 -04:00
Domenico Ottolia
fb00d0f209 Fix bugs with privileged tests 2021-03-25 14:06:05 -04:00
Noah Boorstin
ed37e933e5 busybear: stop NOPing out atomics 
and bump regression to check for 800k instrs, up from 200k
 2021-03-25 13:29:56 -04:00
Jarred Allen
e8e4e1bee2 rv64i linear control flow now working 2021-03-25 13:02:26 -04:00
Jarred Allen
9cbdb44728 Merge branch 'main' into cache 
Conflicts:
	wally-pipelined/src/ifu/ifu.sv
 2021-03-25 00:51:12 -04:00
Teo Ene
1e691e120b Fix typo from last commit 2021-03-24 17:09:58 -05:00
Teo Ene
6a7b69ff2d Updated coremark_bare testbench for IM 2021-03-24 17:04:43 -05:00
Ross Thompson
a768c0406c Updated the function radix to have a new name FunctionName and it now pervents false transisions from the current function name when the PCD is flushed. 2021-03-24 13:03:43 -05:00
Domenico Ottolia
3909158619 re-organize privileged tests to be in rv64p to rv32p folders 2021-03-24 13:51:25 -04:00
Ross Thompson
c7e34bd4a0 added a whole bunch of interseting test code for branches which does not work. 2021-03-23 13:54:59 -05:00
Ross Thompson
9909bdd4d5 Added first benchmark. 2021-03-23 13:54:59 -05:00
Ross Thompson
e6aef66853 Broken commit. Trying to get exe2memfile.pl to work correctly with non 0x8000_0000 starting addresses. 2021-03-23 13:54:59 -05:00
Noah Boorstin
355961f834 busybear: more progress 2021-03-23 14:49:30 -04:00
Noah Boorstin
0dae5401f3 busybear: more progress moving from instrf to instrrawd 2021-03-23 14:06:21 -04:00
Noah Boorstin
7fb2ebec50 busybear: ignore illegal instruction when starting 2021-03-23 13:28:56 -04:00
Noah Boorstin
3c131bb2bd start migrating busybear over to InstrRawD/PCD 
this breaks busybear for now
 2021-03-22 23:45:04 -04:00
Noah Boorstin
1592332d41 Merge branch 'main' into cache 2021-03-22 23:28:30 -04:00
Noah Boorstin
43d23e3d9b busybear: add better warning on illegal instruction 
...also it seems that mret is being picked up as an illegal instruction??
 2021-03-22 18:24:35 -04:00
Noah Boorstin
4160bf50b0 busybear: temporarially force rf[5] correct after failure to read CSR 2021-03-22 18:12:41 -04:00
Noah Boorstin
4be19421c4 busybear: allow overwriting read values 2021-03-22 17:28:44 -04:00
Noah Boorstin
b4166e9fd0 busybear: finally get the right error 2021-03-22 16:52:22 -04:00
Jarred Allen
99fa8beef3 Update icache interface 2021-03-22 15:04:46 -04:00
Noah Boorstin
7350b9f18f busybear: comment out some debug printing 2021-03-22 14:54:05 -04:00
Jarred Allen
507d8ed120 Merge branch 'main' into cache 2021-03-22 14:50:22 -04:00
Noah Boorstin
c4fb51fad1 regression: expect 200k instead of 100k busybear instrs 
and a minor busybear bugfix
 2021-03-22 14:47:52 -04:00
Jarred Allen
bab0e3b90f Change busybear testbench to reflect new location of InstrF 2021-03-20 18:20:27 -04:00
Jarred Allen
e32291bcc2 Put Imperas testbench back 2021-03-20 18:19:51 -04:00
Jarred Allen
665c244ba1 Fix another bug in the icache (why so many of them?) 2021-03-20 17:54:40 -04:00
Jarred Allen
50c961bbe4 Merge changes from main 2021-03-18 18:58:10 -04:00
Shreya Sanghai
804407eab7 fixed minor bugs in testbench 2021-03-18 17:37:10 -04:00
Shreya Sanghai
dfc86539cc Merge branch 'gshare' into main 
Conflicts:
	wally-pipelined/regression/wave.do
 2021-03-18 17:25:48 -04:00
Teo Ene
0ff785549e Switched coremark to RV64IM 2021-03-17 22:39:56 -05:00
Teo Ene
db164462ed adapted coremark bare testbench to new dtim RAM HDL 2021-03-17 16:59:02 -05:00
Jarred Allen
e39ead0460 Merge branch 'main' into cache 
Conflicts:
	wally-pipelined/testbench/testbench-imperas.sv
 2021-03-17 16:40:52 -04:00
Teo Ene
29634f1475 Temporarily reverted my last few commits 2021-03-17 15:16:01 -05:00
Teo Ene
90946d61c5 fix to last commit 2021-03-17 15:02:15 -05:00
Teo Ene
ca901513c8 Added Ross's addr lab stuff to coremark stuff 2021-03-17 14:50:54 -05:00
Elizabeth Hedenberg
bccd37d778 fixing coremark branch prediction 2021-03-17 15:15:55 -04:00
Elizabeth Hedenberg
a3b2ffb2c9 Merge branch '3_3_2021' into main 
Making sure coremark works with spring break changes
 2021-03-17 14:11:37 -04:00
Ross Thompson
0e2352a6de Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-17 11:07:57 -05:00
Ross Thompson
31ad619a21 Added possibly working OSU test bench as a precursor to running a bp benchmark. 
Fixed a few bugs with the function radix.
 2021-03-17 11:06:32 -05:00
Noah Boorstin
45ed2742cf busybear: add seperate message on bad memory access becasue its confusing 2021-03-16 21:42:26 -04:00
Domenico Ottolia
c9d70a1778 Add privileged testbench 2021-03-16 20:28:38 -04:00
Shreya Sanghai
a79e26f9d8 added global history branch predictor 2021-03-16 16:06:40 -04:00
Jarred Allen
662ab53746 Merge remote-tracking branch 'origin/main' into cache 2021-03-15 19:08:25 -04:00
Noah Boorstin
6d8bcfe6bf copy Ross's branch predictor preload change into busybear 2021-03-15 18:27:27 -04:00
Ross Thompson
8e51935082 Converted branch predictor preloads to use system verilog rather than modelsim's load command. 2021-03-15 12:39:44 -05:00
Jarred Allen
003242ae8a Merge upstream changes 2021-03-14 14:57:53 -04:00
Ross Thompson
0edaa625e3 Fixed the issue with the batch mode not working after adding the function radix. 2021-03-12 20:16:03 -06:00
Ross Thompson
ccaaa829ce Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-12 14:58:04 -06:00
David Harris
4465854423 Drafted rv32a tests 2021-03-12 00:06:23 -05:00
David Harris
d4e84c58ed 64-bit AMO debugged 2021-03-11 23:18:33 -05:00
Ross Thompson
b1d1f3995c Improve version of the function radix which does not cause the wave file rendering to slow down. 2021-03-11 17:12:21 -06:00
Noah Boorstin
f31d7a7f5c busybear: account for CSR moving 2021-03-11 06:45:14 +00:00
Jarred Allen
ff48a9e992 Return testbench to normal 2021-03-10 22:58:41 -05:00
Ross Thompson
f1f7884e10 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-10 15:37:02 -06:00
Ross Thompson
149c9aa0f2 Added debug option to disable the function radix if not needed. 
Function radix slows the simulation by 70 to 76 s (8.5%) for the rv64i tests.
 2021-03-10 15:17:02 -06:00
Ross Thompson
4d7e926dbb I finally think I got the function radix debugger working across both 32 and 64 bit applications. 2021-03-10 14:43:44 -06:00
Ross Thompson
7b7cacbaf0 Finally I think I have the function radix mapping across all applications correctly. I still need to clean up the code a bit so it is easier to understand. 2021-03-10 11:00:51 -06:00
Jarred Allen
c0ee17b6ac Merge upstream changes 2021-03-09 21:20:34 -05:00
Jarred Allen
81b29a3891 More progress 2021-03-09 21:16:07 -05:00
David Harris
0baa004bb4 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-09 09:28:32 -05:00
David Harris
bea8ac6d59 WALLY-LRSC atomic test passing 2021-03-09 09:28:25 -05:00
Noah Boorstin
87e2a9b920 busybear: better NOPing out of float instructions 2021-03-08 21:24:19 +00:00
Noah Boorstin
9274d09ae2 busybear: better instrF checking 
So this now checks instrF only when StallD is low. @kaveh I'd love your
opinion on this. I don't know if this is a good idea or not. Ideally we
should probably be checking InstrRawD instead, but I kind of want to stay
checking the instr in the F stage instead of D for now. Idk if this is worth
staying in F, I can't really see any big downsides to checking the instruction in
D except that PCD isn't an external signal, but neither is StallD, so.....
Anyway I'd love others' thoughts on this
 2021-03-08 19:48:12 +00:00
Noah Boorstin
1fc00d41c2 busybear: load mem files from verilog instead of .do 2021-03-08 19:26:26 +00:00
Noah Boorstin
f0a103687e Merge branch 'main' into busybear 2021-03-05 20:27:19 +00:00
Noah Boorstin
464c1de03d busybear: slight testbench update 2021-03-05 19:00:40 +00:00
Ross Thompson
7902c3fdb6 updated the function radix to look at wally signals. 2021-03-04 17:31:12 -06:00
Jarred Allen
5da98b5381 Partial progress towards compressed instructions 2021-03-04 18:30:26 -05:00
Noah Boorstin
cfcd7d1518 busybear: make imperas tests work again 2021-03-04 22:44:49 +00:00
Jarred Allen
b0f4d8e8d4 Remove rd2, working for non-compressed 2021-03-04 16:46:43 -05:00
Noah Boorstin
fde94f9057 Merge branch 'main' into busybear 
Conflicts:
	wally-pipelined/src/uncore/imem.sv
 2021-03-04 20:16:03 +00:00
Ross Thompson
619bbd9d83 Merge branch 'bp' into main 
Concerns:
1. I don't think the correct data buses are going to the multiplier.
2. I'm not sure the FlushF signal is correct.
 2021-03-04 13:35:46 -06:00
bbracker
7852d866ef JALR testing 2021-03-04 10:37:30 -05:00
Teo Ene
27a807db95 Added stop to coremark_bare testbench 2021-03-04 07:47:07 -06:00
Teo Ene
2723b21988 Linux CoreMark and baremetal CoreMark split into two separate tests/configs 2021-03-04 07:44:33 -06:00
Teo Ene
80f6d6c944 Linux CoreMark is operational 2021-03-04 05:58:18 -06:00
Teo Ene
a82a123069 Implemented fix disucssed with Elizabeth 2021-03-03 18:17:53 -06:00
Teo Ene
d3a1afe50e Fix to last push 2021-03-03 15:20:38 -06:00
Noah Boorstin
923489fe16 busybear: probably discovered bug in ahb code 2021-03-01 20:56:04 +00:00
Noah Boorstin
b6dc0a8707 busybear: only check pc when it actually changes 2021-03-01 19:08:35 +00:00
Noah Boorstin
b3247eadd2 busybear: more adapting to new memory system 2021-03-01 18:50:42 +00:00
David Harris
6f4e8b723e Initial (untested) implementation of lr and sc 2021-03-01 00:09:45 -05:00
Noah Boorstin
a267115635 Merge branch 'main' into busybear 2021-02-28 20:45:08 +00:00
Noah Boorstin
932bc0ef85 busybear: check instead of providing InstrF 2021-02-28 16:46:53 +00:00
Noah Boorstin
0596d61a2a busybear: instantiate normal wallypipelinedsoc 2021-02-28 06:02:21 +00:00
Ross Thompson
6191fcb1af Shreya and I found a bug with the exeuction of JAL and JALR instructions. The link was only set in the writeback stage. Once the branch predictor started correctly predicting JAL(R)s the ALU and forwarding logic need to have the PCLinkE at the execution stage in case an instruction in the next two clocks need the data. 2021-02-26 20:12:27 -06:00
Ross Thompson
c2cf3f9fb6 Updating the test bench to include a function radix. Not done. 2021-02-26 19:43:40 -06:00
David Harris
73920282af Eliminated flushing pipeline on CSR reads 2021-02-26 17:00:07 -05:00
kaveh pezeshki
e8b306bcba merged with main to integrate with AHB 2021-02-26 05:37:10 -08:00
Noah Boorstin
4c7b185d90 busybear: add main ram loading, better instr checking also 2021-02-26 20:26:54 +00:00
kaveh Pezeshki
2782ca2480 fixed sensitivity list on error checking always block, removed useless once and for all 2021-02-26 13:41:16 -05:00
kaveh pezeshki
adadc21fc6 restored 2021-02-26 02:22:08 -08:00
David Harris
cd4ba8831c Merged bus into main 2021-02-25 00:28:41 -05:00
Teo Ene
cfd45a46c3 Added provisional coremark files from work with Elizabeth 2021-02-24 20:07:07 -06:00
kaveh pezeshki
251aa982eb condensed always blocks to avoid race conditions 2021-02-24 11:35:28 -08:00
Noah Boorstin
ddaf67c043 busybear: preload bootram 
thanks to Prof Stine for the .do file commands

@kaveh can you check line 201? it does nothing, but things break when
I remove that line
 2021-02-24 18:46:09 +00:00
David Harris
38b8cc652c All tests passing with bus interface 2021-02-24 07:25:03 -05:00
kaveh pezeshki
06f73fe5fe added comments for RAM and bootram, removed trailing whitepace 2021-02-23 21:28:33 -08:00
Noah Boorstin
b7f4e72eec busybear: add bootram section in the same manner as ram 2021-02-24 02:02:28 +00:00
Noah Boorstin
914a36e3e8 busybear: add support for subwords in ram 
this is really weird and i'm not sure if i did it right. I'd love if @kaveh could review it
 2021-02-24 01:51:18 +00:00
Noah Boorstin
7b7e87bd0b busybear: start adding ram 2021-02-23 22:01:23 +00:00
Noah Boorstin
5394d38e4a busybear: remove unused signals 2021-02-23 19:38:19 +00:00
Noah Boorstin
c42c485377 busybear: instantiate soc instead of hart 2021-02-23 18:59:06 +00:00
David Harris
7737b0f709 Fixed fetch stall after jump in bus unit 2021-02-23 09:08:57 -05:00
David Harris
f372e2b8e8 Debugging Bus interface 2021-02-22 13:48:30 -05:00
kaveh pezeshki
e146946e58 Merge remote-tracking branch 'origin/tlb_toy' into busybear 2021-02-22 02:23:01 -08:00
Ross Thompson
7d6093b302 Hacked the sram memory models to reset their internal registers. This allows the simulation to run but is only temporary. 
About 149307ns of simulation run.
 2021-02-18 21:32:15 -06:00
David Harris
a7dd20b388 Multiply instructions working 2021-02-17 15:29:20 -05:00
Noah Boorstin
43f9abdbed busybear testbench: check (almost) all the CSRs 2021-02-16 20:03:24 -05:00
David Harris
adc5d5bc1a Added MUL 2021-02-15 22:27:35 -05:00
Domenico Ottolia
3ee975dd5a Add privileged test cases 2021-02-14 17:01:46 -05:00
Shreya Sanghai
4e887f83a3 added branch tests 2021-02-12 22:40:08 -05:00