310 Commits

Author	SHA1	Message	Date
James E. Stine	694e21541b	Update to FLD/FSD testbench	2021-05-21 09:26:55 -05:00
James E. Stine	474d479280	Update to rv64icfd wally-config to run through FP tests	2021-05-21 09:22:17 -05:00
Katherine Parry	67a41748ba	FMV.D.X imperas test passes	2021-05-20 22:18:33 -04:00
Katherine Parry	71e4a10efb	FMV.D.X imperas test passes	2021-05-20 22:17:59 -04:00
bbracker	114bba8370	small bit of busybear debug progress	2021-05-19 20:18:00 -04:00
bbracker	fd4fae0406	commented out MSTATUS test	2021-05-19 12:38:01 -04:00
James E. Stine	f407bee5ae	Mod to config to properly add FP stuff - for icfd test. Should not change regression test through Imperas as just mod to testbench (add tests64d/tests64f but remove from MISA)	2021-05-18 13:48:44 -05:00
David Harris	7dcc53dcf5	fixed rv64mmu makefile	2021-05-18 14:25:55 -04:00
Katherine Parry	409438bc95	floating point infinite loop removed from imperas tests	2021-05-18 10:42:51 -04:00
bbracker	86d55cd07a	fixed busybear floating point NOP-out feature; restored regression to check 100000 instructions	2021-05-17 19:25:54 -04:00
bbracker	69ef758e78	regression modified to timeout after 10 min \n took Harris\' suggestion for avoiding using ahbliteState package in busybear testbench	2021-05-17 18:44:47 -04:00
James E. Stine	41da78e0b6	Mod Imperas Testbench for updated Div/Rem	2021-05-17 16:56:30 -05:00
Domenico Ottolia	1c884338b0	Forgot to add csr permission tests to testbench	2021-05-04 20:20:22 -04:00
ushakya22	6274c8cb80	Added mip tests to testbench	2021-05-04 15:36:06 -04:00
Domenico Ottolia	14becde792	Re-add medeleg tests to testbench	2021-05-04 14:42:20 -04:00
ushakya22	da352c81e7	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-05-04 02:22:17 -04:00
ushakya22	66344f0604	Added MIE tests to testbench	2021-05-04 02:22:01 -04:00
Domenico Ottolia	2c39c0a6a5	Minor tweaks to mcause & scause tests	2021-05-04 01:33:49 -04:00
David Harris	7c2481bea6	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-05-04 01:19:57 -04:00
David Harris	4db3780ebb	Fixed testbench to produce error when signature.output doesn't exist	2021-05-04 01:19:44 -04:00
Thomas Fleming	39135f221e	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-05-04 01:14:13 -04:00
Domenico Ottolia	1556cc5b9f	Use correct begin_signature for rv64p/MCAUSE and rv64p/SCAUSE	2021-05-04 01:04:12 -04:00
Domenico Ottolia	84911e6345	Fix 32 bit privileged tests!!!	2021-05-04 00:16:19 -04:00
Thomas Fleming	4f5ef65aeb	Restore original order of tests	2021-05-03 23:50:21 -04:00
Thomas Fleming	d53afc8510	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-05-03 23:15:39 -04:00
Thomas Fleming	1f6db293fa	Enable mmu tests in testbench	2021-05-03 23:15:23 -04:00
Domenico Ottolia	12d8ff617b	Run all tests	2021-05-03 22:38:59 -04:00
Domenico Ottolia	353d4e9238	Update cause tests to be longer	2021-05-03 22:38:26 -04:00
Domenico Ottolia	db4e447a25	Add mtvec and stvec tests to testbench	2021-05-03 22:19:50 -04:00
Shriya Nadgauda	c10d332c6e	working testbench-imperas	2021-05-03 22:16:58 -04:00
Shriya Nadgauda	0be6b81df9	finishing merge conflict changes	2021-05-03 22:15:05 -04:00
Shriya Nadgauda	52e0b703b7	merge conflict fixes	2021-05-03 22:12:30 -04:00
Shriya Nadgauda	0282aebec7	updated pipeline tests	2021-05-03 22:07:36 -04:00
Elizabeth Hedenberg	08bfaeffe3	coremark print statment	2021-05-03 19:35:08 -04:00
Elizabeth Hedenberg	800f799b7c	coremark updates	2021-05-03 19:35:07 -04:00
Elizabeth Hedenberg	81ed9b5d06	coremark directory changes	2021-05-03 19:35:06 -04:00
David Harris	699a8f3ac3	Extended maximum signature length to 1M	2021-05-03 15:29:20 -04:00
bbracker	acd99be7f8	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-05-03 09:23:52 -04:00
Noah Boorstin	8d417558ae	busybear: remove now unneeded hack for fixed CSR issue	2021-05-01 15:17:04 -04:00
Katherine Parry	9252d08b41	fpu imperas tests run	2021-05-01 02:18:01 +00:00
bbracker	0d62440f60	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-04-30 06:26:35 -04:00
bbracker	9c08ce5359	rv32 plic test and lint fixes	2021-04-30 06:26:31 -04:00
Domenico Ottolia	830787e3e1	Make vectored interrupt trap handling work, and add tests for mtvec with vectored interrupts	2021-04-29 20:42:14 -04:00
Ross Thompson	893e03d55b	Fixed memory size in configs for rv32ic and rv64ic. ... Removed warning on call to $fscanf.	2021-04-29 17:36:46 -05:00
Domenico Ottolia	750d276feb	Minor improvements to scause test	2021-04-29 16:48:07 -04:00
Domenico Ottolia	fdbd238a87	Add machine-mode timer interrupts to mcause tests	2021-04-29 16:39:18 -04:00
Domenico Ottolia	c9cb2f51d1	Same but don't break sim-wally this time	2021-04-29 15:33:27 -04:00
Domenico Ottolia	fdd4deec2f	Add more exceptions to medeleg tests	2021-04-29 15:32:13 -04:00
ushakya22	f139f248dc	Working MIE timer tests	2021-04-29 15:19:43 -04:00
Domenico Ottolia	99a927be47	Add medeleg tests	2021-04-29 15:02:36 -04:00