Ross Thompson 6191fcb1af Shreya and I found a bug with the exeuction of JAL and JALR instructions. The link was only set in the writeback stage. Once the branch predictor started correctly predicting JAL(R)s the ALU and forwarding logic need to have the PCLinkE at the execution stage in case an instruction in the next two clocks need the data.		2021-02-26 20:12:27 -06:00
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function_radix.sv	Updating the test bench to include a function radix. Not done.	2021-02-26 19:43:40 -06:00
testbench-busybear.sv	Busybear: start checking CSRs	2021-02-02 06:06:03 +00:00
testbench-coremark.sv	Adding coremark testbench and do files that Elizabeth has written thus far, on this account, in order to avoid merge conflicts	2021-02-10 20:48:39 -06:00
testbench-imperas.sv	Shreya and I found a bug with the exeuction of JAL and JALR instructions. The link was only set in the writeback stage. Once the branch predictor started correctly predicting JAL(R)s the ALU and forwarding logic need to have the PCLinkE at the execution stage in case an instruction in the next two clocks need the data.	2021-02-26 20:12:27 -06:00
testbench-peripherals.sv	bus rw bugfix and peripherals testing	2021-02-12 00:02:45 -05:00