mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Moved I-Cache offset selection mux to icache.sv (top level).
When we switch to set associative this is will be more efficient.
This commit is contained in:
Ross Thompson
parent
fdc7c673dd
commit
35afdecda2
@ -184,47 +184,47 @@ add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/N
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add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/D
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add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/Q
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add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/rem0
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add wave -noupdate -group icache -color Orange /testbench/dut/hart/ifu/icache/controller/CurrState
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add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/controller/NextState
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add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/hit
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add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spill
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add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/ICacheStallF
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add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/SavePC
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add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
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add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/UnalignedSelect
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add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/PCMux
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add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
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add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntReset
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add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/PreCntEn
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add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntEn
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add wave -noupdate -group icache -group parameters /testbench/dut/hart/ifu/icache/controller/AHBByteLength
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add wave -noupdate -group icache -group parameters /testbench/dut/hart/ifu/icache/controller/AHBOFFETWIDTH
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add wave -noupdate -group icache -group parameters /testbench/dut/hart/ifu/icache/controller/BlockByteLength
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add wave -noupdate -group icache -group parameters /testbench/dut/hart/ifu/icache/controller/OFFSETWIDTH
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add wave -noupdate -group icache -group parameters /testbench/dut/hart/ifu/icache/controller/WORDSPERLINE
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add wave -noupdate -group icache -group parameters /testbench/dut/hart/ifu/icache/controller/LOGWPL
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add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/FetchCountFlag
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add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/FetchCount
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add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrPAdrF
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add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrReadF
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add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrAckF
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add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrInF
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add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteEnable
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add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteData
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add wave -noupdate -group icache -expand -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/DataValidBit
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add wave -noupdate -group icache -expand -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/DataValid
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add wave -noupdate -group icache -expand -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/DataTag
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add wave -noupdate -group icache -expand -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/cachetags/ReadData
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add wave -noupdate -group icache -expand -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/WriteEnable
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add wave -noupdate -group icache -expand -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/WriteLine
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add wave -noupdate -group icache -expand -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/cachetags/StoredData
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add wave -noupdate -group icache -expand -group {instr to cpu} /testbench/dut/hart/ifu/icache/controller/FinalInstrRawF
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add wave -noupdate -group icache -expand -group {instr to cpu} /testbench/dut/hart/ifu/icache/controller/AlignedInstrRawD
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add wave -noupdate -group icache -expand -group {instr to cpu} /testbench/dut/hart/ifu/icache/controller/FlushDLastCyclen
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add wave -noupdate -group icache -expand -group {instr to cpu} /testbench/dut/hart/ifu/icache/controller/InstrRawD
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add wave -noupdate -group icache -expand -group pc /testbench/dut/hart/ifu/icache/controller/PCPF
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add wave -noupdate -group icache -expand -group pc /testbench/dut/hart/ifu/icache/controller/PCPreFinalF
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add wave -noupdate -group icache -expand -group pc /testbench/dut/hart/ifu/icache/controller/PCPFinalF
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add wave -noupdate -expand -group icache -color Orange /testbench/dut/hart/ifu/icache/controller/CurrState
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add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/controller/NextState
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add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/hit
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add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spill
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add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/ICacheStallF
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add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/SavePC
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add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
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add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/UnalignedSelect
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add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/PCMux
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add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
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add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntReset
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add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/PreCntEn
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add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntEn
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add wave -noupdate -expand -group icache -expand -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/NUMLINES
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add wave -noupdate -expand -group icache -expand -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/BLOCKLEN
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add wave -noupdate -expand -group icache -expand -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/BLOCKBYTELEN
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add wave -noupdate -expand -group icache -expand -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/OFFSETLEN
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add wave -noupdate -expand -group icache -expand -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/INDEXLEN
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add wave -noupdate -expand -group icache -expand -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/TAGLEN
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add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/FetchCountFlag
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add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/FetchCount
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add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrPAdrF
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add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrReadF
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add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrAckF
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add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrInF
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add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteEnable
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add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteData
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add wave -noupdate -expand -group icache -expand -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/DataValidBit
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add wave -noupdate -expand -group icache -expand -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/DataValid
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add wave -noupdate -expand -group icache -expand -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/DataTag
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add wave -noupdate -expand -group icache -expand -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/cachetags/ReadData
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add wave -noupdate -expand -group icache -expand -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/WriteEnable
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add wave -noupdate -expand -group icache -expand -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/WriteLine
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add wave -noupdate -expand -group icache -expand -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/cachetags/StoredData
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add wave -noupdate -expand -group icache -expand -group {instr to cpu} /testbench/dut/hart/ifu/icache/controller/FinalInstrRawF
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add wave -noupdate -expand -group icache -expand -group {instr to cpu} /testbench/dut/hart/ifu/icache/controller/AlignedInstrRawD
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add wave -noupdate -expand -group icache -expand -group {instr to cpu} /testbench/dut/hart/ifu/icache/controller/FlushDLastCyclen
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add wave -noupdate -expand -group icache -expand -group {instr to cpu} /testbench/dut/hart/ifu/icache/controller/InstrRawD
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add wave -noupdate -expand -group icache -expand -group pc /testbench/dut/hart/ifu/icache/controller/PCPF
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add wave -noupdate -expand -group icache -expand -group pc /testbench/dut/hart/ifu/icache/controller/PCPreFinalF
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add wave -noupdate -expand -group icache -expand -group pc /testbench/dut/hart/ifu/icache/controller/PCPFinalF
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/BusState
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/HCLK
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/HRDATA
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@ -245,7 +245,7 @@ add wave -noupdate -group csr -color Aquamarine -label {br executed} -radix unsi
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add wave -noupdate -group csr -color Aquamarine -label {br miss predicted} -radix unsigned {/testbench/dut/hart/priv/csr/genblk1/counters/genblk2/HPMCOUNTER_REGW[4]}
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add wave -noupdate -group csr -childformat {{{/testbench/dut/hart/priv/csr/genblk1/counters/genblk2/HPMCOUNTER_REGW[5]} -radix unsigned} {{/testbench/dut/hart/priv/csr/genblk1/counters/genblk2/HPMCOUNTER_REGW[4]} -radix unsigned}} -subitemconfig {{/testbench/dut/hart/priv/csr/genblk1/counters/genblk2/HPMCOUNTER_REGW[5]} {-height 16 -radix unsigned} {/testbench/dut/hart/priv/csr/genblk1/counters/genblk2/HPMCOUNTER_REGW[4]} {-height 16 -radix unsigned}} /testbench/dut/hart/priv/csr/genblk1/counters/genblk2/HPMCOUNTER_REGW
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TreeUpdate [SetDefaultTree]
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WaveRestoreCursors {{Cursor 4} {32648010 ns} 0} {{Cursor 5} {2172501 ns} 0}
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WaveRestoreCursors {{Cursor 4} {32648010 ns} 0} {{Cursor 5} {759692 ns} 0}
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quietly wave cursor active 2
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configure wave -namecolwidth 250
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configure wave -valuecolwidth 189
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@ -261,4 +261,4 @@ configure wave -griddelta 40
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configure wave -timeline 0
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configure wave -timelineunits ns
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update
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WaveRestoreZoom {0 ns} {391986 ns}
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WaveRestoreZoom {1826338 ns} {1988889 ns}
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68
wally-pipelined/src/cache/ICacheMem.sv
vendored
68
wally-pipelined/src/cache/ICacheMem.sv
vendored
@ -3,77 +3,45 @@
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module ICacheMem #(parameter NUMLINES=512, parameter BLOCKLEN = 256)
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(
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// Pipeline stuff
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input logic clk,
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input logic reset,
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input logic clk,
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input logic reset,
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// If flush is high, invalidate the entire cache
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input logic flush,
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input logic flush,
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// Select which address to read (broken for efficiency's sake)
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input logic [`XLEN-1:0] PCTagF, // physical tag address
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input logic [`XLEN-1:0] PCNextIndexF,
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// Write new data to the cache
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input logic WriteEnable,
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input logic [BLOCKLEN-1:0] WriteLine,
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// Output the word, as well as if it is valid
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output logic [31:0] DataWord, // *** was `XLEN-1
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output logic DataValid
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input logic [`XLEN-1:0] PCTagF, // physical address
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input logic [`XLEN-1:0] PCNextIndexF, // virtual address
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input logic WriteEnable,
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input logic [BLOCKLEN-1:0] WriteLine,
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output logic [BLOCKLEN-1:0] ReadLineF,
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output logic HitF
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);
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// divide the address bus into sections, tag, index, offset
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// divide the address bus into sections; tag, index, and offset
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localparam BLOCKBYTELEN = BLOCKLEN/8;
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localparam OFFSETLEN = $clog2(BLOCKBYTELEN);
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localparam INDEXLEN = $clog2(NUMLINES);
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// *** BUG. `XLEN needs to be replaced with the virtual address width, S32, S39, or S48
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localparam TAGLEN = `XLEN - OFFSETLEN - INDEXLEN;
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// Machinery to read from and write to the correct addresses in memory
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logic [BLOCKLEN-1:0] ReadLine;
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// Machinery to check if a given read is valid and is the desired value
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logic [TAGLEN-1:0] DataTag;
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logic [NUMLINES-1:0] ValidOut;
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logic DataValidBit;
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logic [TAGLEN-1:0] LookupTag;
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logic [NUMLINES-1:0] ValidOut;
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logic DataValidBit;
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// Depth is number of bits in one "word" of the memory, width is number of such words
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sram1rw #(.DEPTH(BLOCKLEN), .WIDTH(NUMLINES))
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cachemem (.*,
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.Addr(PCNextIndexF[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
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.ReadData(ReadLine),
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.ReadData(ReadLineF),
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.WriteData(WriteLine)
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);
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sram1rw #(.DEPTH(TAGLEN), .WIDTH(NUMLINES))
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cachetags (.*,
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.Addr(PCNextIndexF[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
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.ReadData(DataTag),
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.ReadData(LookupTag),
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.WriteData(PCTagF[`XLEN-1:INDEXLEN+OFFSETLEN])
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);
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// Pick the right bits coming out the read line
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//assign DataWord = ReadLineTransformed[ReadOffset];
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//logic [31:0] tempRD;
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always_comb begin
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case (PCTagF[4:1])
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0: DataWord = ReadLine[31:0];
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1: DataWord = ReadLine[47:16];
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2: DataWord = ReadLine[63:32];
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3: DataWord = ReadLine[79:48];
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4: DataWord = ReadLine[95:64];
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5: DataWord = ReadLine[111:80];
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6: DataWord = ReadLine[127:96];
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7: DataWord = ReadLine[143:112];
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8: DataWord = ReadLine[159:128];
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9: DataWord = ReadLine[175:144];
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10: DataWord = ReadLine[191:160];
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11: DataWord = ReadLine[207:176];
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12: DataWord = ReadLine[223:192];
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13: DataWord = ReadLine[239:208];
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14: DataWord = ReadLine[255:224];
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15: DataWord = {16'b0, ReadLine[255:240]};
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endcase
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end
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// Correctly handle the valid bits
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always_ff @(posedge clk, posedge reset) begin
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if (reset) begin
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@ -87,5 +55,5 @@ module ICacheMem #(parameter NUMLINES=512, parameter BLOCKLEN = 256)
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end
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DataValidBit <= ValidOut[PCNextIndexF[INDEXLEN+OFFSETLEN-1:OFFSETLEN]];
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end
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assign DataValid = DataValidBit && (DataTag == PCTagF[`XLEN-1:INDEXLEN+OFFSETLEN]);
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assign HitF = DataValidBit && (LookupTag == PCTagF[`XLEN-1:INDEXLEN+OFFSETLEN]);
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endmodule
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120
wally-pipelined/src/cache/icache.sv
vendored
120
wally-pipelined/src/cache/icache.sv
vendored
@ -25,58 +25,86 @@
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`include "wally-config.vh"
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module icache(
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// Basic pipeline stuff
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input logic clk, reset,
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input logic StallF, StallD,
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input logic FlushD,
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input logic [`XLEN-1:0] PCNextF,
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input logic [`XLEN-1:0] PCPF,
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// Data read in from the ebu unit
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input logic [`XLEN-1:0] InstrInF,
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input logic InstrAckF,
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// Read requested from the ebu unit
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output logic [`XLEN-1:0] InstrPAdrF,
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output logic InstrReadF,
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// High if the instruction currently in the fetch stage is compressed
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output logic CompressedF,
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// High if the icache is requesting a stall
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output logic ICacheStallF,
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// The raw (not decompressed) instruction that was requested
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// If this instruction is compressed, upper 16 bits may be the next 16 bits or may be zeros
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output logic [31:0] InstrRawD
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);
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module icache
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(
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// Basic pipeline stuff
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input logic clk, reset,
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input logic StallF, StallD,
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input logic FlushD,
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input logic [`XLEN-1:0] PCNextF,
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input logic [`XLEN-1:0] PCPF,
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// Data read in from the ebu unit
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input logic [`XLEN-1:0] InstrInF,
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input logic InstrAckF,
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// Read requested from the ebu unit
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output logic [`XLEN-1:0] InstrPAdrF,
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output logic InstrReadF,
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// High if the instruction currently in the fetch stage is compressed
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output logic CompressedF,
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// High if the icache is requesting a stall
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output logic ICacheStallF,
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// The raw (not decompressed) instruction that was requested
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// If this instruction is compressed, upper 16 bits may be the next 16 bits or may be zeros
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output logic [31:0] InstrRawD
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);
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// Configuration parameters
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// TODO Move these to a config file
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localparam integer BLOCKLEN = 256;
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localparam integer NUMLINES = 512;
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// Configuration parameters
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// TODO Move these to a config file
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localparam integer BLOCKLEN = 256;
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localparam integer NUMLINES = 512;
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// Input signals to cache memory
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logic FlushMem;
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logic ICacheMemWriteEnable;
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logic [BLOCKLEN-1:0] ICacheMemWriteData;
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logic EndFetchState;
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logic [`XLEN-1:0] PCTagF, PCNextIndexF;
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// Output signals from cache memory
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logic [31:0] ICacheMemReadData;
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logic ICacheMemReadValid;
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logic ICacheReadEn;
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// Input signals to cache memory
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logic FlushMem;
|
||||
logic ICacheMemWriteEnable;
|
||||
logic [BLOCKLEN-1:0] ICacheMemWriteData;
|
||||
logic EndFetchState;
|
||||
logic [`XLEN-1:0] PCTagF, PCNextIndexF;
|
||||
// Output signals from cache memory
|
||||
logic [31:0] ICacheMemReadData;
|
||||
logic ICacheMemReadValid;
|
||||
logic ICacheReadEn;
|
||||
logic [BLOCKLEN-1:0] ReadLineF;
|
||||
|
||||
|
||||
ICacheMem #(.BLOCKLEN(BLOCKLEN), .NUMLINES(NUMLINES))
|
||||
cachemem(
|
||||
.*,
|
||||
// Stall it if the pipeline is stalled, unless we're stalling it and we're ending our stall
|
||||
.flush(FlushMem),
|
||||
.WriteEnable(ICacheMemWriteEnable),
|
||||
.WriteLine(ICacheMemWriteData),
|
||||
.DataWord(ICacheMemReadData),
|
||||
.DataValid(ICacheMemReadValid)
|
||||
);
|
||||
.*,
|
||||
// Stall it if the pipeline is stalled, unless we're stalling it and we're ending our stall
|
||||
.flush(FlushMem),
|
||||
.WriteEnable(ICacheMemWriteEnable),
|
||||
.WriteLine(ICacheMemWriteData),
|
||||
.ReadLineF(ReadLineF),
|
||||
.HitF(ICacheMemReadValid)
|
||||
);
|
||||
|
||||
ICacheCntrl #(.BLOCKLEN(BLOCKLEN)) controller(.*);
|
||||
always_comb begin
|
||||
case (PCTagF[4:1])
|
||||
0: ICacheMemReadData = ReadLineF[31:0];
|
||||
1: ICacheMemReadData = ReadLineF[47:16];
|
||||
2: ICacheMemReadData = ReadLineF[63:32];
|
||||
3: ICacheMemReadData = ReadLineF[79:48];
|
||||
|
||||
// For now, assume no writes to executable memory
|
||||
assign FlushMem = 1'b0;
|
||||
4: ICacheMemReadData = ReadLineF[95:64];
|
||||
5: ICacheMemReadData = ReadLineF[111:80];
|
||||
6: ICacheMemReadData = ReadLineF[127:96];
|
||||
7: ICacheMemReadData = ReadLineF[143:112];
|
||||
|
||||
8: ICacheMemReadData = ReadLineF[159:128];
|
||||
9: ICacheMemReadData = ReadLineF[175:144];
|
||||
10: ICacheMemReadData = ReadLineF[191:160];
|
||||
11: ICacheMemReadData = ReadLineF[207:176];
|
||||
|
||||
12: ICacheMemReadData = ReadLineF[223:192];
|
||||
13: ICacheMemReadData = ReadLineF[239:208];
|
||||
14: ICacheMemReadData = ReadLineF[255:224];
|
||||
15: ICacheMemReadData = {16'b0, ReadLineF[255:240]};
|
||||
endcase
|
||||
end
|
||||
|
||||
|
||||
ICacheCntrl #(.BLOCKLEN(BLOCKLEN)) controller(.*);
|
||||
|
||||
// For now, assume no writes to executable memory
|
||||
assign FlushMem = 1'b0;
|
||||
endmodule
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user