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mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
cvw/wally-pipelined/src
2021-06-02 10:03:23 -04:00
..
cache Reduced icache to 1 port memory. 2021-05-03 14:47:49 -05:00
dmem fixed InstrValid signals and implemented less costly MEPC loading 2021-06-02 10:03:19 -04:00
ebu Clean up MMU code 2021-05-14 07:12:32 -04:00
fpu Minor cosmetic update to fpu.sv 2021-06-01 15:45:32 -04:00
generic The clock gater was not implemented correctly. Now it is level sensitive to a low clock. 2021-06-01 15:05:22 -05:00
hazard turns out I should not have tried renaming FStallD to FPUStallD because that name was already used! All the same it does feel weird to have two such signals floating around \(ah pun!\) 2021-05-28 23:11:37 -04:00
ieu fixed InstrValid signals and implemented less costly MEPC loading 2021-06-02 10:03:19 -04:00
ifu Forgot to include the new gshare predictor file. 2021-06-01 12:42:03 -05:00
mmu implemented Sv48. 2021-06-01 17:50:37 -04:00
muldiv delete div.bak 2021-06-01 17:39:54 -04:00
privileged fixed InstrValid signals and implemented less costly MEPC loading 2021-06-02 10:03:19 -04:00
uncore plic implementation optimizations 2021-05-19 18:10:48 +00:00
wally fixed InstrValid signals and implemented less costly MEPC loading 2021-06-02 10:03:19 -04:00