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expanded GPIO testing and caught small GPIO bug

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This commit is contained in:
bbracker 2021-06-03 10:03:09 -04:00
parent 987460c49a
commit 8338b3bd34
2 changed files with 8 additions and 2 deletions
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8
wally-pipelined/regression/wave-dos/peripheral-waves.do
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@ -41,15 +41,21 @@ add wave -hex /testbench/dut/hart/ifu/InstrM
add wave -hex /testbench/dut/hart/ieu/c/InstrValidM
add wave /testbench/InstrMName
add wave /testbench/dut/uncore/dtim/memwrite
add wave -hex /testbench/dut/hart/MemPAdrM
add wave -hex /testbench/dut/hart/WriteDataM
add wave -hex /testbench/dut/uncore/HADDR
add wave -hex /testbench/dut/uncore/HWDATA
add wave -hex /testbench/dut/uncore/HRDATA
add wave -hex /testbench/dut/hart/ebu/ReadDataM
add wave -divider
add wave -hex /testbench/PCW
add wave -hex /testbench/InstrW
add wave -hex /testbench/dut/hart/ieu/c/InstrValidW
add wave /testbench/InstrWName
add wave /testbench/dut/hart/ieu/dp/RegWriteW
add wave -hex /testbench/dut/hart/ReadDataW
add wave -hex /testbench/dut/hart/ieu/dp/ResultW
add wave -hex /testbench/dut/hart/ieu/dp/RegWriteW
add wave -hex /testbench/dut/hart/ieu/dp/WriteDataW
add wave -hex /testbench/dut/hart/ieu/dp/RdW
add wave -divider
add wave -hex /testbench/dut/hart/priv/csr/TrapM

2
wally-pipelined/src/uncore/gpio.sv
View File

@ -165,6 +165,6 @@ module gpio (
assign GPIOPinsOut = output_val;
assign GPIOPinsEn = output_en;
assign GPIOIntr = |{(rise_ip & rise_ie),(fall_ip & fall_ip),(high_ip & high_ie),(low_ip & low_ie)};
assign GPIOIntr = |{(rise_ip & rise_ie),(fall_ip & fall_ie),(high_ip & high_ie),(low_ip & low_ie)};
endmodule