Rose Thompson
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068ffda5fb
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Revert "Revert "Trying an experiment. Use the less compact subwordreaddouble in the fpga synthesize rather than subwordreadmisaligned.""
This reverts commit 8136b45ca7.
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2024-03-06 13:28:47 -06:00 |
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Rose Thompson
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c093f53c9c
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Merge branch 'main' of https://github.com/openhwgroup/cvw
Cleaned up the cacheLRU.
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2024-03-05 11:08:40 -06:00 |
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Rose Thompson
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d1a1345e4d
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Merge pull request #644 from davidharrishmc/dev
Synthesis fixes
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2024-03-05 10:39:40 -06:00 |
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Rose Thompson
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e8e0538f6c
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Changed to non-blocking in cacheLRU and removed clearing LRU bits on flush.
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2024-03-05 10:33:47 -06:00 |
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David Harris
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1a0097f6e7
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Further fdivsqrt simplification after starting Sqrt at iteration 0
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2024-03-04 16:40:49 -08:00 |
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David Harris
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9c04df8f69
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2024-03-04 16:04:24 -08:00 |
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David Harris
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2e31bf021c
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Merge pull request #646 from kevindkim723/sqrtbugfix_USLC
Square root R=4 K=2 bug fix
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2024-03-04 16:04:14 -08:00 |
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Rose Thompson
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457d3481e7
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How did this error get past for so long.
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2024-03-04 17:58:41 -06:00 |
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Rose Thompson
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0222e8f42a
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Don't want to clear the lru bits on invalidation (clearvalid).
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2024-03-04 17:52:41 -06:00 |
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Kevin Kim
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10ab07975f
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uslc comments
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2024-03-04 14:31:21 -08:00 |
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Kevin Kim
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9b87a00698
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sqrt mux lint fixes
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2024-03-04 14:31:07 -08:00 |
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Kevin Kim
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587fdbdf8e
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removed j1,j0 from iteration and put inside divider stage
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2024-03-04 14:30:05 -08:00 |
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Kevin Kim
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7dec9cdf21
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optimization in uslc
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2024-03-04 10:46:16 -08:00 |
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Kevin Kim
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9c95cba865
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remove sqrt cycle muxing
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2024-03-03 18:51:10 -08:00 |
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Kevin Kim
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0ff59ff157
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remove redundant mux
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2024-03-03 13:00:20 -08:00 |
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Kevin Kim
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2547e4c6d1
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divider still works with NF+2
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2024-03-03 11:17:51 -08:00 |
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Kevin Kim
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c32173f163
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changed U/C initialization to account for integer bit generation on divider stage for sqrt. Quick and dirty j1 logic fix
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2024-03-03 10:30:18 -08:00 |
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Kevin Kim
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6c24afaf98
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changed cycle count to account for integer bit generation for sqrt
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2024-03-03 10:29:32 -08:00 |
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Kevin Kim
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c45d67f8ba
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fdivsqrt changes
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2024-03-02 20:29:03 -08:00 |
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Kevin Kim
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77ccc7b319
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removed square root pre-process muxes
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2024-03-02 15:55:34 -08:00 |
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Rose Thompson
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a22de45631
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Removed unused storedelay from align.
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2024-03-02 16:20:31 -06:00 |
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Rose Thompson
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8136b45ca7
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Revert "Trying an experiment. Use the less compact subwordreaddouble in the fpga synthesize rather than subwordreadmisaligned."
This reverts commit cba3209e7f.
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2024-03-02 11:55:43 -06:00 |
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Rose Thompson
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cba3209e7f
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Trying an experiment. Use the less compact subwordreaddouble in the fpga synthesize rather than subwordreadmisaligned.
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2024-03-02 11:38:33 -06:00 |
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Rose Thompson
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4c3d927474
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Renamed CacheHit to Hit.
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2024-03-01 11:00:24 -06:00 |
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Rose Thompson
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60f96112db
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Moved the zero stage boot loader to the fpga directory.
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2024-03-01 10:23:55 -06:00 |
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Rose Thompson
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e72880fd89
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Changed cachefsm state STATE_HIT to STATE_ACCESS.
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2024-03-01 09:59:54 -06:00 |
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Rose Thompson
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85691f0e8b
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Simplified and clarified names in cacheLRU.
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2024-02-29 17:18:01 -06:00 |
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Rose Thompson
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90ad5e7dab
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Updated the cache for book clarity.
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2024-02-28 17:07:32 -06:00 |
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David Harris
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90e89ced1d
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Fixes for synthesis. HPTW change will break x detection
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2024-02-26 04:20:08 -08:00 |
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Rose Thompson
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252ca5b925
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Merge branch 'main' of https://github.com/openhwgroup/cvw
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2024-02-23 14:11:18 -06:00 |
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Rose Thompson
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ab750e150f
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Fixed lint errors for alignment.
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2024-02-23 14:00:19 -06:00 |
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Rose Thompson
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a2d5618d88
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Added sdc to pma allow shift.
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2024-02-23 13:46:04 -06:00 |
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Rose Thompson
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e84b7cc147
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Cleanup.
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2024-02-23 13:00:21 -06:00 |
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Rose Thompson
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ae36f1e5a5
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Merge branch 'main' of github.com:ross144/cvw
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2024-02-23 09:43:03 -06:00 |
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Rose Thompson
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caac48b7f2
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Removed duplicate endianswap.
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2024-02-23 09:42:39 -06:00 |
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Rose Thompson
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a402883115
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Simplifications of subword code.
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2024-02-23 09:41:59 -06:00 |
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Kevin Kim
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b487477ecd
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modified synth makefile to handle derived configs
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2024-02-22 19:40:06 -08:00 |
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Rose Thompson
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fbc18abaa0
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Siginficant cleanup of subwordwritemisaligned.
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2024-02-22 14:17:15 -06:00 |
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Rose Thompson
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45c30267a5
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Cleanup.
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2024-02-22 14:08:04 -06:00 |
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Rose Thompson
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69d31d50e2
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Updated subword misaligned.
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2024-02-22 13:29:39 -06:00 |
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Rose Thompson
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6ed2376582
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Merge pull request #641 from kevindkim723/regression-softfloat
updated softfloat configs list in regression-wally
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2024-02-22 12:26:52 -06:00 |
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Kevin Kim
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dd88b4765a
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updated configs list in regression-wally
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2024-02-22 10:22:23 -08:00 |
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Rose Thompson
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d90bd9dee7
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Merge pull request #639 from kevindkim723/regression-softfloat
added softfloat support to regression-wally
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2024-02-22 12:19:21 -06:00 |
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Rose Thompson
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7e1ea1e6d9
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Beginning subword cleanup.
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2024-02-22 09:37:16 -06:00 |
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Rose Thompson
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1ece6f8eae
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Swapped to the more compact subwordreadmisaligned.sv.
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2024-02-22 09:34:16 -06:00 |
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Rose Thompson
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3714b2bf4a
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Non-ideal fix. Added new output from pma which indicates if the write shift should occur.
The more ideal solution would be to have the pma indicate if the shift should occur and the maximum amount..
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2024-02-22 09:14:43 -06:00 |
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Kevin Kim
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02081cac40
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softfloat jobs now run concurrently with help of testfloat-batch.do directing compiled designs into individual folders for each config/test
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2024-02-21 20:49:38 -08:00 |
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Rose Thompson
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6a9c2d8dc4
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Closer to getting subword write misaligned working.
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2024-02-20 20:23:42 -06:00 |
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Kevin Kim
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19a61e301e
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formatting
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2024-02-20 17:24:15 -08:00 |
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Kevin Kim
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7e3df23f28
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Revert "formatting"
This reverts commit c8ff1bddec.
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2024-02-20 17:24:04 -08:00 |
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