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https://github.com/openhwgroup/cvw
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Merge pull request #646 from kevindkim723/sqrtbugfix_USLC
Square root R=4 K=2 bug fix
This commit is contained in:
David Harris
GitHub
commit
2e31bf021c
@ -94,7 +94,7 @@ localparam LOGR = $clog2(RADIX); // r = log(R
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localparam RK = LOGR*DIVCOPIES; // r*k bits per cycle generated
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// intermediate division parameters not directly used in fdivsqrt hardware
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localparam FPDIVMINb = NF + 3; // minimum length of fractional part: Nf result bits + guard and round bits + 1 extra bit to allow sqrt being shifted right
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localparam FPDIVMINb = NF + 2; // minimum length of fractional part: Nf result bits + guard and round bits + 1 extra bit to allow sqrt being shifted right
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//localparam FPDIVMINb = NF + 2 + (RADIX == 2); // minimum length of fractional part: Nf result bits + guard and round bits + 1 extra bit for preshifting radix2 square root right, if radix4 doesn't use a right shift. This version saves one cycle on double-precision with R=4,k=4. However, it doesn't work yet because C is too short, so k is incorrectly calculated as a 1 in the lsb after the last step.
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localparam DIVMINb = ((FPDIVMINb<XLEN) & IDIV_ON_FPU) ? XLEN : FPDIVMINb; // minimum fractional bits b = max(XLEN, FPDIVMINb)
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localparam RESBITS = DIVMINb + LOGR; // number of bits in a result: r integer + b fractional
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@ -71,8 +71,7 @@ module fdivsqrtcycles import cvw::*; #(parameter cvw_t P) (
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// The datapath produces rk bits per cycle, so Cycles = ceil (ResultBitsE / rk)
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always_comb begin
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if (SqrtE) FPResultBitsE = Nf + 2 + 0; // Nf + two fractional bits for round/guard; integer bit implicit because starting at n=1
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else FPResultBitsE = Nf + 2 + P.LOGR; // Nf + two fractional bits for round/guard + integer bits
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FPResultBitsE = Nf + 2 + P.LOGR; // Nf + two fractional bits for round/guard; integer bit implicit because starting at n=1
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if (P.IDIV_ON_FPU) ResultBitsE = IntDivE ? IntResultBitsE : FPResultBitsE;
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else ResultBitsE = FPResultBitsE;
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@ -72,20 +72,19 @@ module fdivsqrtiter import cvw::*; #(parameter cvw_t P) (
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// UOTFC Result U and UM registers/initialization mux
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// Initialize U to 1.0 and UM to 0 for square root; U to 0 and UM to -1 otherwise
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assign initU = {SqrtE, {(P.DIVb){1'b0}}};
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assign initUM = {~SqrtE, {(P.DIVb){1'b0}}};
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assign initU ={(P.DIVb+1){1'b0}};
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assign initUM = {{1'b1}, {(P.DIVb){1'b0}}};
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mux2 #(P.DIVb+1) Umux(UNext[P.DIVCOPIES-1], initU, IFDivStartE, UMux);
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mux2 #(P.DIVb+1) UMmux(UMNext[P.DIVCOPIES-1], initUM, IFDivStartE, UMMux);
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flopen #(P.DIVb+1) UReg(clk, FDivBusyE, UMux, U[0]);
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flopen #(P.DIVb+1) UMReg(clk, FDivBusyE, UMMux, UM[0]);
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// C register/initialization mux
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// Initialize C to -1 for sqrt and -R for division
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logic [1:0] initCUpper;
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if(P.RADIX == 4) begin
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mux2 #(2) cuppermux4(2'b00, 2'b11, SqrtE, initCUpper);
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assign initCUpper = 2'b00;
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end else begin
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mux2 #(2) cuppermux2(2'b10, 2'b11, SqrtE, initCUpper);
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assign initCUpper = 2'b10;
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end
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assign initC = {initCUpper, {P.DIVb{1'b0}}};
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@ -108,9 +107,7 @@ module fdivsqrtiter import cvw::*; #(parameter cvw_t P) (
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.WS(WS[i]), .WC(WC[i]), .WSNext(WSNext[i]), .WCNext(WCNext[i]),
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.C(C[i]), .U(U[i]), .UM(UM[i]), .CNext(C[i+1]), .UNext(UNext[i]), .UMNext(UMNext[i]), .un(un[i]));
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end else begin: stage
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logic j1;
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assign j1 = (i == 0 & ~C[0][P.DIVb-1]);
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fdivsqrtstage4 #(P) fdivsqrtstage(.D, .DBar, .D2, .DBar2, .SqrtE, .j1,
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fdivsqrtstage4 #(P) fdivsqrtstage(.D, .DBar, .D2, .DBar2, .SqrtE,
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.WS(WS[i]), .WC(WC[i]), .WSNext(WSNext[i]), .WCNext(WCNext[i]),
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.C(C[i]), .U(U[i]), .UM(UM[i]), .CNext(C[i+1]), .UNext(UNext[i]), .UMNext(UMNext[i]), .un(un[i]));
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end
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@ -174,9 +174,7 @@ module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) (
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logic [P.DIVb:0] PreSqrtX;
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assign EvenExp = Xe[0] ^ ell[0]; // effective unbiased exponent after normalization is even
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mux2 #(P.DIVb+1) sqrtxmux(Xnorm, {1'b0, Xnorm[P.DIVb:1]}, EvenExp, PreSqrtX); // X if exponent odd, X/2 if exponent even
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if (P.RADIX == 2) assign SqrtX = {3'b111, PreSqrtX}; // PreSqrtX - 2 = 2(PreSqrtX/2 - 1)
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else assign SqrtX = {2'b11, PreSqrtX, 1'b0}; // 2PreSqrtX - 4 = 4(PreSqrtX/2 - 1)
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mux2 #(P.DIVb+4) sqrtxmux({4'b0,Xnorm[P.DIVb:1]}, {5'b00, Xnorm[P.DIVb:2]}, EvenExp, SqrtX); // X/2 if exponent odd, X/4 if exponent even
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/*
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// Attempt to optimize radix 4 to use a left shift by 1 or zero initially, followed by no more left shift
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@ -32,7 +32,7 @@ module fdivsqrtstage4 import cvw::*; #(parameter cvw_t P) (
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input logic [P.DIVb:0] U,UM, // U1.DIVb
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input logic [P.DIVb+3:0] WS, WC, // Q4.DIVb
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input logic [P.DIVb+1:0] C, // Q2.DIVb
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input logic SqrtE, j1,
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input logic SqrtE,
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output logic [P.DIVb+1:0] CNext, // Q2.DIVb
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output logic un,
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output logic [P.DIVb:0] UNext, UMNext, // U1.DIVb
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@ -48,13 +48,16 @@ module fdivsqrtstage4 import cvw::*; #(parameter cvw_t P) (
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logic [7:0] WCmsbs, WSmsbs; // U4.4
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logic CarryIn;
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logic [P.DIVb+3:0] WSA, WCA; // Q4.DIVb
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logic j0,j1;
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// Digit Selection logic
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assign j0 = ~C[P.DIVb+1]; // first step of R digit selection: C = 00...0
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assign j1 = C[P.DIVb] ^ C[P.DIVb-1]; // second step of R digit selection: C = 1100...0
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assign Smsbs = U[P.DIVb:P.DIVb-4]; // U1.4 most significant bits of square root
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assign Dmsbs = D[P.DIVb-1:P.DIVb-3]; // U0.3 most significant fractional bits of divisor after leading 1
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assign WCmsbs = WC[P.DIVb+3:P.DIVb-4]; // Q4.4 most significant bits of residual
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assign WSmsbs = WS[P.DIVb+3:P.DIVb-4]; // Q4.4 most significant bits of residual
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fdivsqrtuslc4cmp uslc4(.Dmsbs, .Smsbs, .WSmsbs, .WCmsbs, .SqrtE, .j1, .udigit);
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fdivsqrtuslc4cmp uslc4(.Dmsbs, .Smsbs, .WSmsbs, .WCmsbs, .SqrtE, .j1, .j0, .udigit);
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assign un = 1'b0; // unused for radix 4
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// F generation logic
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@ -31,7 +31,8 @@ module fdivsqrtuslc4cmp (
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input logic [2:0] Dmsbs, // U0.3 fractional bits after implicit leading 1
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input logic [4:0] Smsbs, // U1.4 leading bits of square root approximation
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input logic [7:0] WSmsbs, WCmsbs, // Q4.4 residual most significant bits
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input logic SqrtE, j1,
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input logic SqrtE,
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input logic j0,j1, // are we on first (j0) or second step (j1) of digit selection
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output logic [3:0] udigit // {2, 1, -1, -2} digit is 0 if none are hot
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);
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logic [6:0] Wmsbs;
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@ -46,7 +47,9 @@ module fdivsqrtuslc4cmp (
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// Wmsbs = | |
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logic [6:0] mk2, mk1, mk0, mkm1;
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logic [6:0] mkj2, mkj1, mkj0, mkjm1;
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logic [6:0] mks2[7:0], mks1[7:0];
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logic sqrtspecial;
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// Prepopulate table of mks0
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assign mks2[0] = 12;
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@ -65,20 +68,26 @@ module fdivsqrtuslc4cmp (
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assign mks1[5] = 8; // is the logic any cheaper if this is a 6?
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assign mks1[6] = 8;
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assign mks1[7] = 8;
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// handles special case when j = 0 or j = 1 for sqrt
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assign mkj2 = 20; // when j = 1 use mk2[101] when j = 0 use anything bigger than 7.
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assign mkj1 = j1 ? 8 : 0; // when j = 1 use mk1[101] = 8 and when j = 0 use 0 so we choose u_0 = 1
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assign sqrtspecial = SqrtE & (j1 | j0);
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// Choose A for current operation
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// Choose A for current operation
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always_comb
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if (SqrtE) begin
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if (j1) A = 3'b101;
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else if (Smsbs == 5'b10000) A = 3'b111;
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if (Smsbs[4]) A = 3'b111; // *** can we get rid of SMSBs case?
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else A = Smsbs[2:0];
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end else A = Dmsbs;
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// Choose selection constants based on a
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assign mk2 = mks2[A];
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assign mk1 = mks1[A];
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assign mk0 = -mks1[A];
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assign mkm1 = (A == 3'b000) ? -13 : -mks2[A]; // asymmetry in table
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assign mk2 = sqrtspecial ? mkj2 : mks2[A];
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assign mk1 = sqrtspecial ? mkj1 : mks1[A];
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assign mk0 = -mk1;
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assign mkm1 = (A == 3'b000) ? -13 : -mk2; // asymmetry in table *** can we hide?
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// Compare residual W to selection constants to choose digit
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always_comb
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@ -51,7 +51,8 @@ configs: $(CONFIG)
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$(CONFIG):
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@echo $(CONFIG)
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cp -r $(OLDCONFIGDIR)/shared/*.vh $(CONFIGDIR)
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cp -r $(OLDCONFIGDIR)/$(CONFIG)/* $(CONFIGDIR)
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# cp -r $(OLDCONFIGDIR)/$(CONFIG)/* $(CONFIGDIR)
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cp -r $(OLDCONFIGDIR)/deriv/$(CONFIG)/* $(CONFIGDIR)
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# adjust DTIM and IROM to reasonable values depending on config
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ifneq ($(filter $(CONFIG), $(DIRS32)),)
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@ -61,8 +62,8 @@ else ifneq ($(filter $(CONFIG), $(DIRS64)),)
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sed -i "s/DTIM_RANGE.*/DTIM_RANGE = 56\'h01FF;/g" $(CONFIGDIR)/config.vh
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sed -i "s/IROM_RANGE.*/IROM_RANGE = 56\'h01FF;/g" $(CONFIGDIR)/config.vh
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else
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$(info $(CONFIG) does not exist in $(DIRS32) or $(DIRS64))
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@echo "Config not in list, RAM_RANGE will be unmodified"
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$(info $(CONFIG) does not exist in $(DIRS32) or $(DIRS64))
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@echo "Config not in list, RAM_RANGE will be unmodified"
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endif
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# if USESRAM = 1, set that in the config file, otherwise reduce sizes
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