Katherine Parry
|
70968a4ec3
|
FSD and FLD imperas tests pass
|
2021-05-23 18:33:14 -04:00 |
|
bbracker
|
846553ac7d
|
improved PLIC test organization
|
2021-05-21 15:13:02 -04:00 |
|
James E. Stine
|
e70136ec78
|
Minor testbench updates to rv64icfd
|
2021-05-21 09:41:21 -05:00 |
|
James E. Stine
|
23769e36a5
|
Update to testbench-imperase for rv64icfd
|
2021-05-21 09:28:44 -05:00 |
|
James E. Stine
|
fed3b30557
|
Update to FLD/FSD testbench
|
2021-05-21 09:26:55 -05:00 |
|
James E. Stine
|
c89d3e01bb
|
Update to rv64icfd wally-config to run through FP tests
|
2021-05-21 09:22:17 -05:00 |
|
Katherine Parry
|
4db7f3065c
|
FMV.D.X imperas test passes
|
2021-05-20 22:18:33 -04:00 |
|
Katherine Parry
|
06af239e6c
|
FMV.D.X imperas test passes
|
2021-05-20 22:17:59 -04:00 |
|
bbracker
|
979a9bf037
|
commented out MSTATUS test
|
2021-05-19 12:38:01 -04:00 |
|
James E. Stine
|
44dc665fc5
|
Mod to config to properly add FP stuff - for icfd test. Should not change regression test through Imperas as just mod to testbench (add tests64d/tests64f but remove from MISA)
|
2021-05-18 13:48:44 -05:00 |
|
David Harris
|
26531f2634
|
fixed rv64mmu makefile
|
2021-05-18 14:25:55 -04:00 |
|
Katherine Parry
|
9464c9022d
|
floating point infinite loop removed from imperas tests
|
2021-05-18 10:42:51 -04:00 |
|
James E. Stine
|
daf780b9c2
|
Mod Imperas Testbench for updated Div/Rem
|
2021-05-17 16:56:30 -05:00 |
|
Domenico Ottolia
|
88ab07d456
|
Forgot to add csr permission tests to testbench
|
2021-05-04 20:20:22 -04:00 |
|
ushakya22
|
682bc7b58e
|
Added mip tests to testbench
|
2021-05-04 15:36:06 -04:00 |
|
Domenico Ottolia
|
8398e653dd
|
Re-add medeleg tests to testbench
|
2021-05-04 14:42:20 -04:00 |
|
ushakya22
|
46f20745d7
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2021-05-04 02:22:17 -04:00 |
|
ushakya22
|
b805b98a8c
|
Added MIE tests to testbench
|
2021-05-04 02:22:01 -04:00 |
|
Domenico Ottolia
|
1673ad6e27
|
Minor tweaks to mcause & scause tests
|
2021-05-04 01:33:49 -04:00 |
|
David Harris
|
45b0af497c
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2021-05-04 01:19:57 -04:00 |
|
David Harris
|
d68fe44446
|
Fixed testbench to produce error when signature.output doesn't exist
|
2021-05-04 01:19:44 -04:00 |
|
Thomas Fleming
|
41a19153cc
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2021-05-04 01:14:13 -04:00 |
|
Domenico Ottolia
|
67c7bfe34d
|
Use correct begin_signature for rv64p/MCAUSE and rv64p/SCAUSE
|
2021-05-04 01:04:12 -04:00 |
|
Domenico Ottolia
|
973f32da47
|
Fix 32 bit privileged tests!!!
|
2021-05-04 00:16:19 -04:00 |
|
Thomas Fleming
|
a3b5ae9742
|
Restore original order of tests
|
2021-05-03 23:50:21 -04:00 |
|
Thomas Fleming
|
ad40464557
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2021-05-03 23:15:39 -04:00 |
|
Thomas Fleming
|
803a69efe6
|
Enable mmu tests in testbench
|
2021-05-03 23:15:23 -04:00 |
|
Domenico Ottolia
|
2669a6a0db
|
Run all tests
|
2021-05-03 22:38:59 -04:00 |
|
Domenico Ottolia
|
4d70e22a6a
|
Update cause tests to be longer
|
2021-05-03 22:38:26 -04:00 |
|
Domenico Ottolia
|
997c9ad5c0
|
Add mtvec and stvec tests to testbench
|
2021-05-03 22:19:50 -04:00 |
|
Shriya Nadgauda
|
780ad3eaf4
|
working testbench-imperas
|
2021-05-03 22:16:58 -04:00 |
|
Shriya Nadgauda
|
c5a306426a
|
finishing merge conflict changes
|
2021-05-03 22:15:05 -04:00 |
|
Shriya Nadgauda
|
b7159652f6
|
merge conflict fixes
|
2021-05-03 22:12:30 -04:00 |
|
Shriya Nadgauda
|
968994c04a
|
updated pipeline tests
|
2021-05-03 22:07:36 -04:00 |
|
David Harris
|
d7438929d4
|
Extended maximum signature length to 1M
|
2021-05-03 15:29:20 -04:00 |
|
bbracker
|
2368b58cc9
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2021-05-03 09:23:52 -04:00 |
|
Katherine Parry
|
db95151d8d
|
fpu imperas tests run
|
2021-05-01 02:18:01 +00:00 |
|
bbracker
|
1fcd43e844
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2021-04-30 06:26:35 -04:00 |
|
bbracker
|
182bfdbb0e
|
rv32 plic test and lint fixes
|
2021-04-30 06:26:31 -04:00 |
|
Domenico Ottolia
|
d03ca20dc9
|
Make vectored interrupt trap handling work, and add tests for mtvec with vectored interrupts
|
2021-04-29 20:42:14 -04:00 |
|
Domenico Ottolia
|
c60c4f4adc
|
Minor improvements to scause test
|
2021-04-29 16:48:07 -04:00 |
|
Domenico Ottolia
|
c8a81779ca
|
Add machine-mode timer interrupts to mcause tests
|
2021-04-29 16:39:18 -04:00 |
|
Domenico Ottolia
|
6fc04768f5
|
Same but don't break sim-wally this time
|
2021-04-29 15:33:27 -04:00 |
|
Domenico Ottolia
|
7ae5d4d11e
|
Add more exceptions to medeleg tests
|
2021-04-29 15:32:13 -04:00 |
|
ushakya22
|
77210527c1
|
Working MIE timer tests
|
2021-04-29 15:19:43 -04:00 |
|
Domenico Ottolia
|
4fae8088e3
|
Add medeleg tests
|
2021-04-29 15:02:36 -04:00 |
|
Ross Thompson
|
72363f5c66
|
Added the ability to exclude branch predictor.
|
2021-04-26 14:27:42 -05:00 |
|
Ross Thompson
|
8e5409af66
|
Icache integrated!
Merge branch 'icache-almost-working' into main
|
2021-04-26 11:48:58 -05:00 |
|
bbracker
|
31a0387136
|
merge cleanup; mem init is broken
|
2021-04-26 08:00:17 -04:00 |
|
Ross Thompson
|
6e803b724e
|
Merge branch 'tests' into icache-almost-working
|
2021-04-25 21:25:36 -05:00 |
|
Shriya Nadgauda
|
c66e63ff70
|
adding pipeline testing
|
2021-04-23 14:19:17 -04:00 |
|
Ross Thompson
|
020fb65adf
|
Fixed icache for 32 bit.
Merge branch 'cache' into main
|
2021-04-22 16:45:29 -05:00 |
|
Thomas Fleming
|
6acaa313b5
|
Temporarily disable rv64 mmu test
Will restore once cache revamp is pushed
|
2021-04-22 13:19:18 -04:00 |
|
Domenico Ottolia
|
44da1488ff
|
Add tests for stval and mtval
|
2021-04-21 02:31:32 -04:00 |
|
Domenico Ottolia
|
f63f16f486
|
Add tests for scause, and improve tests for sepc. Also make improvements to privileged test generator run.sh file
|
2021-04-21 01:12:55 -04:00 |
|
Domenico Ottolia
|
bf86a809eb
|
Add tests for sepc register
|
2021-04-20 23:50:53 -04:00 |
|
Ross Thompson
|
251ece20fe
|
Broken icache. Design is done. Time to debug.
|
2021-04-20 19:55:49 -05:00 |
|
Jarred Allen
|
850f728cc7
|
Merge branch 'main' into cache
|
2021-04-19 00:05:23 -04:00 |
|
bbracker
|
290b3424e5
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2021-04-15 21:09:27 -04:00 |
|
bbracker
|
368c94d4ff
|
working GPIO interrupt demo
|
2021-04-15 21:09:15 -04:00 |
|
Domenico Ottolia
|
9f13ee3f31
|
Add tests for scause and ucause
|
2021-04-15 19:41:25 -04:00 |
|
Domenico Ottolia
|
531423d7e1
|
Add 32 bit privileged tests
|
2021-04-15 16:55:39 -04:00 |
|
Jarred Allen
|
81c02bda55
|
Merge branch 'main' into cache
|
2021-04-15 13:47:19 -04:00 |
|
Thomas Fleming
|
3c49fd08f6
|
Remove imem from testbenches
|
2021-04-14 20:20:34 -04:00 |
|
Jarred Allen
|
c1e2e58ebe
|
Merge branch 'main' into cache
Conflicts:
wally-pipelined/src/cache/dmapped.sv
wally-pipelined/src/cache/line.sv
wally-pipelined/src/ifu/icache.sv
|
2021-04-14 18:24:32 -04:00 |
|
bbracker
|
8f7ddcfdff
|
rv64 interrupt servicing
|
2021-04-14 10:19:42 -04:00 |
|
Jarred Allen
|
fc8b8ad7aa
|
A few more cache fixes
|
2021-04-13 01:07:40 -04:00 |
|
Jarred Allen
|
d99b8f772e
|
Merge from branch 'main'
|
2021-04-08 17:19:34 -04:00 |
|
bbracker
|
1ee8feffe5
|
integrated peripheral testing into existing workflow
|
2021-04-08 15:31:39 -04:00 |
|
bbracker
|
755e2e5771
|
merge testbench
|
2021-04-08 14:28:01 -04:00 |
|
Domenico Ottolia
|
65abe13f4f
|
Cause an Illegal Instruction Exception when attempting to write readonly CSRs
|
2021-04-08 05:12:54 -04:00 |
|
Thomas Fleming
|
303c2c4839
|
Implement support for superpages
|
2021-04-08 02:44:59 -04:00 |
|
Ross Thompson
|
4322694f7a
|
Switch to use RV64IC for the benchmarks.
Still not working correctly with the icache.
instr
addr correct got
|
2021-04-07 19:12:43 -05:00 |
|
Domenico Ottolia
|
60cf38192b
|
Add privileged tests to testbench
|
2021-04-07 02:22:08 -04:00 |
|
Domenico Ottolia
|
465d3986b0
|
Add passing mtval and mepc tests
|
2021-04-07 02:21:05 -04:00 |
|
Ross Thompson
|
c91436d3b7
|
Merge branch 'icache_bp_bug' into tests
Not sure this merge is right.
|
2021-04-06 21:46:40 -05:00 |
|
Ross Thompson
|
bff2d61a1f
|
Steps to getting branch predictor benchmarks running.
|
2021-04-06 21:20:51 -05:00 |
|
Thomas Fleming
|
dbd5a4320e
|
Merge branch 'mmu' into main
Conflicts:
wally-pipelined/src/wally/wallypipelinedhart.sv
|
2021-04-03 22:12:52 -04:00 |
|
Thomas Fleming
|
8dfec29f7e
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2021-04-03 22:09:50 -04:00 |
|
Katherine Parry
|
d7b1379ab8
|
Integrated FPU
|
2021-04-03 20:52:26 +00:00 |
|
James E. Stine
|
0595ae983f
|
Put back imperas testbench until figure out why m_supported is running for rv64ic
|
2021-04-02 08:19:25 -05:00 |
|
James E. Stine
|
cff08adc3a
|
Added some updates to divider - still not working all the time. Still a bug with signals within muldiv - specificaly MultDivE being modified during Execute stage. Seems to be triggered by ahblite signal.
|
2021-04-02 06:27:37 -05:00 |
|
Thomas Fleming
|
fdb20ee1cf
|
Implement sfence.vma and fix tlb writing
|
2021-04-01 15:55:05 -04:00 |
|
Ross Thompson
|
a64a37d702
|
Merge of main with the new icache and the branch predictor. I believe there is a bug in the icache with unaligned memory access. The second part of the access is incorrectly relying on the PCF being the address of the next two bytes of the instruction. However this is not always the case as the branch predictor can get the wrong target address. The icache needs to generate the +2 address internally.
|
2021-03-30 23:18:20 -05:00 |
|
Thomas Fleming
|
eca2427f94
|
Merge remote-tracking branch 'origin/main' into main
Bring icache and MMU code together
Conflicts:
wally-pipelined/src/ifu/ifu.sv
wally-pipelined/testbench/testbench-imperas.sv
|
2021-03-30 22:24:47 -04:00 |
|
Thomas Fleming
|
7126ab7864
|
Complete basic page table walker
|
2021-03-30 22:19:27 -04:00 |
|
Thomas Fleming
|
0994d03b28
|
Update virtual memory tests and move to separate folder
|
2021-03-30 22:18:29 -04:00 |
|
Domenico Ottolia
|
f7cbaeb217
|
Add one more test to WALLY-CAUSE, and update privileged testgen
|
2021-03-30 19:44:58 -04:00 |
|
Domenico Ottolia
|
6619a5f44f
|
Add mcause tests to testbench
|
2021-03-30 17:17:59 -04:00 |
|
ushakya22
|
6b9ae41302
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2021-03-30 15:25:07 -04:00 |
|
Jarred Allen
|
631454ccf9
|
Merge branch 'cache2' into cache
Conflicts:
wally-pipelined/testbench/testbench-imperas.sv
|
2021-03-30 13:32:33 -04:00 |
|
Jarred Allen
|
6e83ccc3c4
|
Comment out failing tests
|
2021-03-30 13:07:26 -04:00 |
|
Jarred Allen
|
108f18e580
|
Merge branch 'cache' into main
|
2021-03-30 12:56:19 -04:00 |
|
Jarred Allen
|
7ca57cc4fc
|
Merge branch 'main' into cache
Conflicts:
wally-pipelined/regression/wave-dos/ahb-waves.do
wally-pipelined/src/ifu/ifu.sv
wally-pipelined/testbench/testbench-busybear.sv
wally-pipelined/testbench/testbench-imperas.sv
|
2021-03-30 12:55:01 -04:00 |
|
David Harris
|
8723fb916c
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2021-03-26 13:04:52 -04:00 |
|
David Harris
|
637bba6509
|
Added fp test to testbench
|
2021-03-26 13:03:23 -04:00 |
|
Shreya Sanghai
|
cc988f420f
|
removed minor bugs
|
2021-03-25 20:29:50 -04:00 |
|
ShreyaSanghai
|
139c2076a1
|
Removed PCW and InstrW from ifu
|
2021-03-26 01:53:19 +05:30 |
|
Jarred Allen
|
3b4f0141f4
|
Begin work on compressed instructions
|
2021-03-25 14:43:10 -04:00 |
|
Jarred Allen
|
602271ff7b
|
rv64i linear control flow now working
|
2021-03-25 13:02:26 -04:00 |
|