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725 Commits

Author SHA1 Message Date
Skylar Litz
64a537c59b Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-27 10:50:19 -07:00
Skylar Litz
f2b6842edb fix AttemptedInstructionCount from ground zero 2022-04-27 10:45:40 -07:00
David Harris
515270a8cf Added torture.tv test vectors 2022-04-27 13:08:36 +00:00
David Harris
cce0a421be Checked in torture.tv 2022-04-27 13:06:24 +00:00
David Harris
9d82232c14 Cleaned up canonical NaNs and removed denorm outputs in baby_torture.tv 2022-04-26 19:41:30 +00:00
Kip Macsai-Goren
4b00531d77 fixed incorrect configs in regression 2022-04-25 19:28:47 +00:00
Kip Macsai-Goren
74b103fae4 added working tests to test list, updated regression for new configs 2022-04-25 19:18:15 +00:00
Kip Macsai-Goren
33875b20b5 fixed initial value, timing on fs bits changing after floating point instruction 2022-04-25 19:17:29 +00:00
Kip Macsai-Goren
2e0f45eab4 removed atomic, floating point from privileged tests configs 2022-04-25 19:13:15 +00:00
Kip Macsai-Goren
01f8bdfafc added new tests to tests.vh, comented out until they pass regression 2022-04-25 18:22:44 +00:00
Kip Macsai-Goren
992cedbc52 Lowered WFI timeout wait time for privileged configs 2022-04-25 17:47:10 +00:00
David Harris
0957b7040d Restored MPRV behavior per spec 2022-04-25 14:52:18 +00:00
David Harris
1a8369b02b Added dummy mstatus byte endianness fields tied to 0, mstatush register, removed UIE and UPIE depricated fields 2022-04-25 14:49:00 +00:00
David Harris
142636173e Added MTINST hardwired to 0, and added timeout of U-mode WFI 2022-04-24 20:00:02 +00:00
David Harris
28e8aa4f97 Fixed InstrMisalignedFaultM mtval 2022-04-24 17:31:30 +00:00
David Harris
ffecdda6e6 Improved priority order and mtval of traps to match spec 2022-04-24 17:24:45 +00:00
David Harris
04b0579b89 Extended sim time to fully boot Linux. Added comments to hazard unit 2022-04-24 13:51:00 +00:00
Kip Macsai-Goren
bd87af478a Changed mtval for instruction misaligned fault to get address from ieuAdrM (Jal/branch target address) 2022-04-22 22:46:11 +00:00
bbracker
9eec1a83a6 deprecate unused LINUX_FIX_READ macro 2022-04-21 19:14:47 -07:00
bbracker
9c1e398bb5 change how tristate I/O is spoofed in GPIO loopback test 2022-04-21 10:31:16 -07:00
Ross Thompson
e56b9f18d5 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-21 09:52:42 -05:00
Ross Thompson
a86274a1e0 Modified wally-pipelined.do for no trace linux sim. 2022-04-21 09:52:33 -05:00
David Harris
1e19cf9f14 Simplified profile for UART boot; added warnings on UART Rx errors 2022-04-21 04:54:45 +00:00
Kip Macsai-Goren
25d0f6305a added new tests to tests.vh 2022-04-20 17:34:40 +00:00
Kip Macsai-Goren
8e72ace5ac fixed rv32ia to support clint and GPIO for priv tests 2022-04-20 17:31:34 +00:00
Kip Macsai-Goren
324d3fcea5 added working general trap tests to regression 2022-04-20 06:48:01 +00:00
Ross Thompson
b94927d8a6 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-19 14:09:50 -05:00
David Harris
c57b9e6703 Added baby torture tests 2022-04-19 15:13:06 +00:00
David Harris
eaa0d44980 Fixed WFI decoding in IFU 2022-04-18 19:02:08 +00:00
Kip Macsai-Goren
ced763beb6 Added GPIO loopback to let outputs cause interrupts 2022-04-18 07:22:49 +00:00
Kip Macsai-Goren
121cc627f6 Added working trap test to regression, fixed hanfling of some interrupts 2022-04-18 07:22:16 +00:00
Shreya Sanghai
6f0085201b replaced k with bpred size 2022-04-18 04:21:03 +00:00
Shreya Sanghai
a8b3cc8cf9 added bpred size to wally config 2022-04-18 04:21:03 +00:00
David Harris
22842816a8 LSU name cleanup 2022-04-18 03:18:38 +00:00
Ross Thompson
61dbf13a69 Fixed bug I introduced by csrc cleanup and changes to ILA. 2022-04-17 21:45:46 -05:00
David Harris
e04febdb57 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-04-18 01:30:11 +00:00
David Harris
c07b9d1722 Renamed FinalAMOWriteDataM to AMOWriteDataM 2022-04-18 01:30:03 +00:00
David Harris
6504017044 Run 4M instructions in buildroot test to get through kernel & VirtMem startup 2022-04-18 01:29:38 +00:00
Ross Thompson
a5d4e39e7d Added back the instret counter to ILA. 2022-04-17 18:44:07 -05:00
Ross Thompson
3add26be64 fixed no forcing bug in linux testbench. 2022-04-17 17:49:51 -05:00
David Harris
d8b4c985cd Remvoed bytemask anding from FinalWriteDataM in subwordwrite 2022-04-17 22:33:25 +00:00
David Harris
6bb4cd1bca Prefix comparator cleanup 2022-04-17 21:53:11 +00:00
David Harris
5bb521635e Experiments with prefix comparator; minor fixes in WFI and testbench warnings 2022-04-17 21:43:12 +00:00
Kip Macsai-Goren
331efcedc4 added new tests to makefrag and tests.vh 2022-04-17 21:00:36 +00:00
Ross Thompson
5a6ad32688 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-17 15:23:46 -05:00
Ross Thompson
7135364d1a Increased uart baud rate to 230400. 
Added uart signals to debugger.
 2022-04-17 15:23:39 -05:00
David Harris
b4902a6ff9 First implementation of WFI timeout wait 2022-04-17 17:20:35 +00:00
David Harris
6769f0cb43 Added comments in fcvt 2022-04-17 16:53:10 +00:00
David Harris
d71940d96d Simplified SLT logic 2022-04-17 16:49:51 +00:00
Ross Thompson
55c667b60d Commented output power analysis to speed simulation. 2022-04-16 15:32:59 -05:00
Ross Thompson
f8bdb6db49 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-16 14:59:03 -05:00
Ross Thompson
bfc68bef69 Fixed possible bugs in LRSC. 2022-04-16 14:45:31 -05:00
David Harris
0932d4df46 Added WFI support to IFU to keep it in the pipeline 2022-04-14 17:26:17 +00:00
David Harris
c3bca40e05 Added WFI to the testbench instruction name decoder 2022-04-14 17:12:11 +00:00
David Harris
6e16922aae WFI should set EPC to PC+4 2022-04-14 17:05:22 +00:00
bbracker
0e183be3e5 fix testbench timing bug where interrupt forcing didn't happen soon enough because it was waiting on StallM 2022-04-14 09:23:21 -07:00
bbracker
489ce4269a fix ReadDataM forcing 2022-04-13 15:32:00 -07:00
Ross Thompson
65573f07b7 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-13 13:39:47 -05:00
bbracker
c697c17b05 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-13 05:35:56 -07:00
bbracker
016e960401 change interrupt spoofing to happen at negative clock edges 2022-04-13 04:31:23 -07:00
bbracker
3465d8cd32 improve testbench-linux.sv to correctly load in PLIC IntEnable checkpoint and to handle edge case where interrupt is caused by enabling interrupts in SSTATUS 2022-04-13 03:37:53 -07:00
bbracker
67ef47b25b whoops forgot to update AttemptedInstructionCount in interrupt spoofing 2022-04-13 00:49:37 -07:00
bbracker
6c3d274970 change testbench-linux to by default use attempted instruction count for warning/error messages 2022-04-12 21:22:08 -07:00
Ross Thompson
2eb2263e94 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-12 19:38:04 -05:00
Ross Thompson
adb4e30c45 Missed the force on uart for no tracking. 2022-04-12 19:37:44 -05:00
Ross Thompson
d087deef65 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-12 17:56:48 -05:00
Ross Thompson
22f2e88553 UART and clock speed changes to support 30Mhz. 2022-04-12 17:56:36 -05:00
Ross Thompson
396f697d2f Hacky fix to prevent ITLBMissF and TrapM bug. 2022-04-12 17:56:23 -05:00
Ross Thompson
70e207e010 Found the complex TrapM giving back the wrong instruction bug. 
As I was reviewing the busfsm I found a typo.

  assign UnCachedLSUBusRead = (BusCurrState == STATE_BUS_READY & UnCachedAccess & LSURWM[1] & IgnoreRequest) |
							  (BusCurrState == STATE_BUS_UNCACHED_READ);

It should be

  assign UnCachedLSUBusRead = (BusCurrState == STATE_BUS_READY & UnCachedAccess & LSURWM[1] & ~IgnoreRequest) |
							  (BusCurrState == STATE_BUS_UNCACHED_READ);

There is a ~ missing before IgnoreRequest. I restarted the FPGA and had it trigger on the specific faulting event.  Sure enough the bus makes an IFUBusRead, which UncachedLSUBusRead feeds into.   The specific instruction in the fetch stage had an ITLBMiss with a physical address in an unmapped area which is interpreted as an uncached operation.  IgnoreRequest is is high if there is a TrapM | ITLBMissF.  Without the & ~IgnoreRequest the invalid address translation makes the request.
 2022-04-11 13:07:52 -05:00
Ross Thompson
56bea58a3c Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-10 13:41:27 -05:00
Ross Thompson
fc5eac6820 Modified the linux test bench to take a new parameter which can run simulation from 470M out to login prompt. This shouldn't break the regression test or checkpointing. 2022-04-10 13:27:54 -05:00
bbracker
c0c5733a1d upgrade testbench interrupt forcing such that first m_timer interrupt now successfully spoofs 2022-04-08 13:45:27 -07:00
bbracker
23406d0926 small signs of life on new interrupt spoofing 2022-04-08 12:32:30 -07:00
Ross Thompson
de868ef3a2 Possible fix for trap concurent with xret. Fixes the priority so trap has higher priority than either sret or mret. Previous code had priority to xret in the trap logic and privilege logic, but not the csrsr logic. This caused partial execution of the instruction. 2022-04-07 16:56:28 -05:00
Ross Thompson
1614996941 Fixed typo in tests.vh 2022-04-07 16:28:28 -05:00
Katherine Parry
74e0db04ac fixed errors and warnings in rv32e 2022-04-07 17:21:20 +00:00
Kip Macsai-Goren
c3a6b88acc updated test signature locations 2022-04-06 07:28:38 +00:00
Kip Macsai-Goren
fbcb0c0bd8 Added missing ZFH macro to new configs 2022-04-06 07:13:51 +00:00
David Harris
7f462a6168 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-04-05 23:23:47 +00:00
David Harris
23da303ad3 Added bootmem source ccode 2022-04-05 23:22:53 +00:00
Ross Thompson
900939581e Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-05 15:42:07 -05:00
Ross Thompson
5faa88acd5 Increazed fpga clock speed to 35Mhz. 
linux boot is much faster.
 2022-04-05 15:09:49 -05:00
Katherine Parry
c3d07b2c46 generating all testfloat vectors 2022-04-04 17:17:12 +00:00
Ross Thompson
91e99f0d34 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-04 10:56:10 -05:00
Ross Thompson
077beb18dd Constraint changes for 40Mhz wally. 2022-04-04 10:50:48 -05:00
Ross Thompson
b77201143f Updated the bootloader to use the flash card divider. This will allow wally to run at a faster speed than flash. 2022-04-04 10:38:37 -05:00
Ross Thompson
400b5f7632 Fixed the SDC clock divider so it actually can work during reset. This will enable the fpga to operate at a faster clock while the SDC is < 10Mhz. 2022-04-04 09:57:26 -05:00
Ross Thompson
38160fe6ea Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-03 17:56:55 -05:00
Ross Thompson
3ebb7f1057 fpga simulation works again. 2022-04-03 17:31:07 -05:00
David Harris
fb95767da0 Fixed bug with CSRRS/CSRRC for MIP/SIP 2022-04-03 20:18:25 +00:00
Ross Thompson
3db60a1cc1 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-02 16:39:54 -05:00
Ross Thompson
2376d66ec2 Added more ILA signals. 2022-04-02 16:39:45 -05:00
Kip Macsai-Goren
37c755e6ce added RV64IA config to have a config without compressed instructions 2022-04-02 18:24:08 +00:00
Ross Thompson
691f1a6b0d Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-01 17:18:25 -05:00
Ross Thompson
51dfa16f59 Updated the fpga test bench. 2022-04-01 17:14:47 -05:00
Ross Thompson
48c49802b2 Fixed linting issues. 2022-04-01 15:20:45 -05:00
Ross Thompson
301f20052b Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-01 12:50:34 -05:00
Ross Thompson
19a8df9739 Added wave config 
added new signals to ILA.
 2022-04-01 12:44:14 -05:00
bbracker
9d26bfe71d expand WALLY-PERIPH test to use SEIP on PLIC context 1 2022-03-31 18:02:06 -07:00
bbracker
e09079d8b4 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-31 17:54:43 -07:00
bbracker
55df8bc3f7 fix lingering overrun error bug 2022-03-31 17:54:32 -07:00
Ross Thompson
48c862d536 Added PLIC to ILA. 2022-03-31 16:44:49 -05:00
Ross Thompson
da93d14050 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-31 16:30:55 -05:00
Ross Thompson
b5cdf035fc Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-31 15:50:04 -05:00
Ross Thompson
ade4a4cd5e Notes on what to change in ram.sv. 2022-03-31 15:48:15 -05:00
bbracker
bdb3417656 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-31 13:46:32 -07:00
bbracker
0f7e995055 simplify plic logic 2022-03-31 13:46:24 -07:00
David Harris
c7043e4d63 Added SystemVerilog flag to fma.do so that fma16 compiles properly 2022-03-31 17:00:38 +00:00
Ross Thompson
88c5cdc873 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-31 11:39:41 -05:00
Ross Thompson
bf9683f0d2 Forced to go back to hard coded preload. 2022-03-31 11:39:37 -05:00
Ross Thompson
54001222cf Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-31 11:38:55 -05:00
Ross Thompson
285fc6fd4d Modified clint to support all byte write sizes. 2022-03-31 11:31:52 -05:00
David Harris
dd3af17b3f Added synthesis script for fma16 2022-03-31 00:51:33 +00:00
David Harris
3457c6e512 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-03-30 23:06:36 +00:00
bbracker
69a0f6e00b big interrupts refactor 2022-03-30 13:22:41 -07:00
Ross Thompson
0a5b500aca Changed sram1p1rw to have the same type of bytewrite enables as bram. 2022-03-30 11:38:25 -05:00
David Harris
9b1f85d353 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-03-30 16:26:27 +00:00
David Harris
08fad856e3 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-03-30 16:13:42 +00:00
Ross Thompson
e4f4e1bd43 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-30 11:09:44 -05:00
Ross Thompson
f52ab01362 Partial cleanup of memories. 2022-03-30 11:09:21 -05:00
Ross Thompson
839bede656 Converted over to the blockram/sram memories. Now I just need to cleanup. But before the cleanup I wan to make sure the FPGA synthesizes with these changes and actually keeps the preload. 2022-03-30 11:04:15 -05:00
Ross Thompson
997c1b87fe rv32gc and rv64gc now use the updated ram3.sv (will rename to ram.sv) which uses a vivado block ram compatible memory. Still need to update simpleram.sv to use this block ram compatible memory. 2022-03-29 23:48:19 -05:00
Ross Thompson
66e9380cfb Partial fix to allow byte write enables with fpga and still get a preload to work. 2022-03-29 19:12:29 -05:00
Kip Macsai-Goren
d031c003ba fixed arch bge test signature output location after update 2022-03-29 20:45:18 +00:00
David Harris
03fa9084bc Updated synthesis to look at fma16.v, other scripts to use fma16.v instead of fma16.sv 2022-03-29 19:16:41 +00:00
David Harris
c4f2c6b110 fpu compare simplification, minor cleanup 2022-03-29 17:11:28 +00:00
Kip Macsai-Goren
56a0542405 made machine timer bit of IP registers unwriteable so it can only change when the interrupt actually changes 2022-03-29 02:26:42 +00:00
Kip Macsai-Goren
a6d90a25c2 fixed signature location of the new periph with no compressed instructions 2022-03-29 02:15:17 +00:00
bbracker
8ea25e591b fix typo that Madeleine found 2022-03-28 15:39:29 -07:00
Kip Macsai-Goren
709f8e6e0d fixed double multiplication on vectored interrupts 2022-03-28 19:12:31 +00:00
Kip Macsai-Goren
eb337fd3e1 added test config that doesn't use compressed instructions for privileged tests 2022-03-28 19:12:31 +00:00
Skylar Litz
f91fb7a388 add AtemptedInstructionCount signal 2022-03-26 21:28:57 +00:00
Skylar Litz
62a330c290 update to match new filesystem organization 2022-03-26 21:28:32 +00:00
Kip Macsai-Goren
7ae1d14191 added basic trap tests that do not pass regression yet. updated signature adresses 2022-03-25 22:57:41 +00:00
Ross Thompson
61c714ebe6 I think this version of csri matches what is required in the spec. ExtIntS should not be written into the SEIP register bit. 2022-03-25 13:10:31 -05:00
Ross Thompson
fe896bff8e Found a way to remove a bus input into MMU. PAdr can be made into VAdr by selecting the faulting virtual address when writing the DTLB. 2022-03-24 23:47:28 -05:00
bbracker
6f6663cd67 fix multiple-context PLIC checkpoint generation 2022-03-25 01:02:22 +00:00
bbracker
d33de3ef6b tabs vs spaces disagreement 2022-03-24 17:11:41 -07:00
bbracker
4b376e2834 1st attempt at multiple channel PLIC 2022-03-24 17:08:10 -07:00
Ross Thompson
71aad2d213 Moved WriteDataM register into LSU. 2022-03-23 14:17:59 -05:00
Ross Thompson
8f74fd2a50 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-23 14:10:38 -05:00
Katherine Parry
7cf994526a fixed typo in unpack.sv 2022-03-23 18:26:59 +00:00
Ross Thompson
aa60b57fb3 Cleanup in testbench-linux.sv. 2022-03-22 22:34:38 -05:00
Ross Thompson
33b9b5423d reverted temporary change to configs. 2022-03-22 22:31:34 -05:00
Katherine Parry
fcd23a006e fixed lint error in fpudivsqrtrecur.sv 2022-03-23 03:24:41 +00:00
Ross Thompson
849707f161 Switched csri IP_REGW to use assignements rather than always_comb as this is incompatible with forcing. 2022-03-22 22:04:06 -05:00
Ross Thompson
c233ef9768 Reverted change to configuration which caused issue with lint. 2022-03-22 21:44:08 -05:00
Ross Thompson
b2487f4b72 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-22 21:28:50 -05:00
Ross Thompson
4ca9458534 added SIP, SIE, and SSTATUS to checkpoints. Can't seem to get the linux testbench to force SIP. 2022-03-22 21:28:34 -05:00
Katherine Parry
23adb2dd03 unpack.sv cleanup 2022-03-23 01:53:37 +00:00
Ross Thompson
e6b42cb10f Added spoof of uart addresses +0x2 and +0x6. 2022-03-22 16:52:27 -05:00
Ross Thompson
ca8fb45367 Added comment about needed fix to misaligned fault. 2022-03-22 16:52:07 -05:00
Katherine Parry
e3d01c875b FMA parameterized and FMA testbench reworked 2022-03-19 19:39:03 +00:00
Ross Thompson
ee4b38dce3 dtim writes are supressed on non cacheable operation. 2022-03-12 00:46:11 -06:00
Ross Thompson
86cc758354 cleanup of ram.sv 2022-03-11 18:09:22 -06:00
Ross Thompson
7a25d577ba Added new asserts to testbench. 2022-03-11 15:41:53 -06:00
Ross Thompson
67ff8f27f4 Can now support the following memory and bus configurations. 
1. dtim/irom only
2. bus only
3. dtim/irom + bus
4. caches + bus
 2022-03-11 15:18:56 -06:00
Ross Thompson
9dce2a0679 Towards allowing dtim + bus. 2022-03-11 14:58:21 -06:00
Ross Thompson
6e24a807f6 mild cleanup. 2022-03-11 13:05:47 -06:00
Ross Thompson
b7a680ec2a Moved subcachelineread inside the cache. There is some ugliness to still resolve. 2022-03-11 12:44:04 -06:00
Ross Thompson
a18f06c20b Moved subcacheline read inside the cache. 2022-03-11 11:03:36 -06:00
Ross Thompson
52cc852600 removed unused parameter. 2022-03-11 10:43:54 -06:00
Ross Thompson
7f0c5cc847 atomic cleanup. 2022-03-10 18:56:37 -06:00
Ross Thompson
257015a2df Name changes. 2022-03-10 18:50:03 -06:00
Ross Thompson
6d914def08 Name cleanup. 2022-03-10 18:44:50 -06:00
Ross Thompson
63b1ea88c9 Signal name cleanup. 2022-03-10 18:26:58 -06:00
Ross Thompson
654c4d1148 simplified uncore's name for HWDATA. 2022-03-10 18:17:44 -06:00
Ross Thompson
1aa87c9f3a Moved subwordwrite to lsu directory. 2022-03-10 18:15:25 -06:00
Ross Thompson
d0cf41dbe4 Simplified byte write enable logic. 2022-03-10 18:13:35 -06:00
Ross Thompson
396c97fc36 Byte write enables are passing all configs now. 2022-03-10 17:26:32 -06:00
Ross Thompson
d8e71e8e35 Progress on the path to getting all configs working with byte write enables. 2022-03-10 17:02:52 -06:00
Ross Thompson
67ef46ea92 Partially working byte write enables. Works for cache, but not dtim or bus only. 2022-03-10 16:11:39 -06:00
Ross Thompson
7a129c75cd Added byte write enables to cache SRAMs. 2022-03-10 15:48:31 -06:00
David Harris
bc2b757952 bit write update 2022-03-09 19:09:20 +00:00
David Harris
27f09ffb33 Refactored SRAM bit write enable 2022-03-09 17:49:28 +00:00
David Harris
89e0830883 Updated testbench to read expected flags 2022-03-09 13:58:17 +00:00
Ross Thompson
95bb4cc8a8 Minor cleanup to interlockfsm. 2022-03-08 23:38:58 -06:00
Ross Thompson
9b113149b6 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-08 18:05:35 -06:00
Ross Thompson
0310fe858f Comments. 2022-03-08 18:05:25 -06:00
Ross Thompson
75e93baaee Marked signals for name changes. 2022-03-08 17:41:02 -06:00
David Harris
00908132e6 Added more test cases and rounding modes to fma test generator 2022-03-08 23:29:29 +00:00
David Harris
8fa6a85af2 fixed setup.sh merge conflict 2022-03-08 23:21:06 +00:00
David Harris
c8f2dce026 fma16_testgen.c test cases 2022-03-08 23:18:18 +00:00
Ross Thompson
3ec32d7ce8 Removed unused signal. 2022-03-08 16:58:26 -06:00
Ross Thompson
d78ba777a4 Added parameter to spillsupport. 2022-03-08 16:38:48 -06:00
Ross Thompson
7b96b3f73c Moved cacheable signal into cache. 2022-03-08 16:34:02 -06:00
bbracker
742e8d98cd fix up PLIC and UART checkpointing 2022-03-07 23:48:47 -08:00
bbracker
92e1583db5 change testbench-linux.sv to use new shared location of disassembly files 2022-03-07 20:04:08 -08:00
David Harris
7391c6d338 Checked in fma16_template.v 2022-03-06 13:29:35 +00:00
David Harris
e4d18f1808 removed more old 64priv tests 2022-03-04 03:57:19 +00:00
bbracker
41c75dc89d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-03-04 00:12:00 +00:00
bbracker
c3e59ae2df comment out nonfunctioning CSR-PERMISSIONS-M test 2022-03-04 00:11:55 +00:00
David Harris
a50f1a4424 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-03-04 00:07:34 +00:00
David Harris
2cea3349ad LSU/Cache code review notes 2022-03-04 00:07:31 +00:00
bbracker
d645666fe7 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-03-04 00:06:27 +00:00
bbracker
79ff8d3c80 remove imperas32p tests 2022-03-04 00:06:18 +00:00
David Harris
6431ad4a8b Fixed fma files to stop breaking synthesis. Changed Makefiles to skip Imperas 2022-03-03 15:38:08 +00:00
David Harris
f76e396255 erge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-03-02 23:47:16 +00:00
David Harris
8e83aaeced fma file fixes 2022-03-02 23:47:01 +00:00
bbracker
87aad1d953 fix peripheral test and add it to regression 2022-03-02 23:44:39 +00:00