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2,852 Commits 14 Branches 1 Tag 31 MiB
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237 Commits

Author SHA1 Message Date
David Harris
de5e80696d Cleaned up synthesis warnings 2022-02-11 01:15:16 +00:00
Ross Thompson
689c32215f Fixed bugs in ifu spills and missing reset on bus data register. 2022-02-10 18:11:57 -06:00
Ross Thompson
5fd22caed4 Replacement policy cleanup. 2022-02-10 11:42:40 -06:00
Ross Thompson
f716cce832 Replacement policy cleanup. 2022-02-10 11:40:10 -06:00
Ross Thompson
104a9acf81 Cleanup. 2022-02-10 11:27:15 -06:00
Ross Thompson
fdb4f909fc Cleanup + critical path optimizations. 2022-02-10 11:11:16 -06:00
Ross Thompson
88c7a94aa9 Cache name clarifications. 2022-02-10 10:50:17 -06:00
Ross Thompson
32eee5a06a More cache cleanup. 2022-02-10 10:43:37 -06:00
Ross Thompson
91f2b5adf5 structural muxes. 2022-02-09 19:36:21 -06:00
Ross Thompson
7ff715f44f More cache cleanup. 2022-02-09 19:29:15 -06:00
Ross Thompson
754bd41fde Cleaned up comments. 2022-02-09 19:21:35 -06:00
Ross Thompson
36ab78ef3b Removed all possilbe paths to PreSelAdr from TrapM. 2022-02-09 19:20:10 -06:00
Ross Thompson
7810a09782 Annotated the final changes required to move sram address off the critial path. 2022-02-08 18:17:31 -06:00
Ross Thompson
30d6514661 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-08 17:52:15 -06:00
Ross Thompson
4a7ebb3757 Cache cleanup write enables. 2022-02-08 17:52:09 -06:00
Ross Thompson
bdb3794d5e Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-08 15:43:18 -06:00
Ross Thompson
c2907ec0f4 Cleanup IFU. 2022-02-08 14:54:53 -06:00
Ross Thompson
038897f448 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-08 14:47:15 -06:00
Ross Thompson
4273775a2b Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-08 14:22:19 -06:00
Ross Thompson
e02bc8db67 rv32e works for now. Still need to optimize. 2022-02-08 14:21:55 -06:00
Ross Thompson
f211fe635a Moved some muxes back into the bp. 2022-02-08 14:17:44 -06:00
David Harris
1479762ae9 RAM simplification 2022-02-08 20:15:23 +00:00
Ross Thompson
aa12d90272 Temporary commit which gets the no branch predictor implementation working. 2022-02-08 14:13:55 -06:00
Ross Thompson
8a2ee22395 Finished merge. 2022-02-08 11:36:24 -06:00
Ross Thompson
e2191e3637 Preparing to make a major change to the cache's write enables. 2022-02-08 09:47:01 -06:00
David Harris
c61cd55c5c Merged TIM and regular testbenches. RV32e now working and back in regression. 2022-02-08 12:18:13 +00:00
Ross Thompson
5c9e23527d cachefsm cleanup. 2022-02-07 22:09:56 -06:00
Ross Thompson
da2dca9816 Removed VDWriteEnable. 2022-02-07 21:59:18 -06:00
Ross Thompson
161f907cae more partial cleanup of fsm and write enables. 2022-02-07 17:41:56 -06:00
Ross Thompson
359a23237d Progress towards simplifying the cache's write enables. 2022-02-07 17:23:09 -06:00
Ross Thompson
188fe28691 more cleanup. 2022-02-07 13:29:19 -06:00
Ross Thompson
9510a33c15 More cachefsm cleanup. 2022-02-07 13:19:37 -06:00
Ross Thompson
708e0cf183 More cachefsm cleanup. 2022-02-07 12:30:27 -06:00
Ross Thompson
5539a5fa6f More cachefsm cleanup. 2022-02-07 11:16:20 -06:00
Ross Thompson
6668956351 More cachefsm cleanup. 2022-02-07 11:12:28 -06:00
Ross Thompson
5536e3ca90 More cachefsm cleanup. 2022-02-07 10:54:22 -06:00
Ross Thompson
529d8b629a Cache cleanup. 2022-02-07 10:43:58 -06:00
Ross Thompson
41a79556e0 More cachfsm cleanup. 2022-02-07 10:33:50 -06:00
David Harris
99f3d7a7f6 Reverted cache change 2022-02-07 14:47:20 +00:00
David Harris
45dc9c1ae6 Cache syntax cleanup 2022-02-07 14:43:24 +00:00
Ross Thompson
0b66106925 More cachefsm cleanup. 2022-02-06 21:50:44 -06:00
Ross Thompson
dd6baa9ed4 started cachefsm cleanup. 2022-02-06 21:39:38 -06:00
David Harris
9b55848ffc Added E tests to wally-riscv-arch-test rv32i_m/I and fixed cyclic path in rv32e configuration 2022-02-06 01:22:40 +00:00
Ross Thompson
d21be9d998 Added config to allow using the save/restore or replay implementation to handle sram clocked read delay. 2022-02-04 23:49:07 -06:00
Ross Thompson
ea84211ff9 Removed unused ports from caches and buses. 2022-02-04 22:52:51 -06:00
Ross Thompson
011ad09341 Cleanup. 2022-02-04 22:40:51 -06:00
Ross Thompson
4074f695e0 Moved the hwdata mux back into the busdp. 2022-02-04 22:39:13 -06:00
Ross Thompson
40eb055861 Merged together the two sub cache line read muxes. 
One mux was used for loads and the other for eviction.
 2022-02-04 22:30:04 -06:00
David Harris
72bc64ef28 Temporarily changed rv32e config to use TIM, but it still fails. Added rv32e tests. 2022-02-05 04:16:18 +00:00
Ross Thompson
290430cda8 Moved the sub cache line read logic to lsu/ifu. 2022-02-04 20:42:53 -06:00
Ross Thompson
725852362e Got separate module for the sub cache line read. 2022-02-04 20:23:09 -06:00
Ross Thompson
cdd599e340 Second optimization of save/restore. 2022-02-04 14:35:12 -06:00
Ross Thompson
459054900f Optimization of cache save/restore. 2022-02-04 14:21:04 -06:00
Ross Thompson
7c1f7e335c Working first cut of the cache changes moving the replay to a save/restore. 
The current implementation is too expensive costing (tag+linelen)*numway flip flops and muxes.
 2022-02-04 13:31:32 -06:00
David Harris
ee3300bcd2 sram1rw cleanup 2022-02-03 18:03:22 +00:00
David Harris
97d31cec21 sram1rw cleanup 2022-02-03 17:50:23 +00:00
David Harris
f9dd79d3e3 cachereplacementpolicy cleanup 2022-02-03 17:19:14 +00:00
David Harris
034ff5462c cachereplacementpolicy cleanup 2022-02-03 17:18:48 +00:00
David Harris
65f3bf4e0a cacheway cleanup 2022-02-03 16:52:22 +00:00
David Harris
eef04eed84 cacheway cleanup 2022-02-03 16:33:01 +00:00
David Harris
4d09510af9 cacheway cleanup 2022-02-03 16:07:55 +00:00
David Harris
7f237220dd cacheway cleanup 2022-02-03 16:00:57 +00:00
David Harris
a6708ed887 cache cleanup 2022-02-03 15:36:11 +00:00
David Harris
38bbe23d14 More config file cleanup; 32ic tests broken 2022-02-03 01:08:34 +00:00
David Harris
da8819d64b changed DMEM and IMEM configurations to support BUS/TIM/CACHE 2022-02-03 00:41:09 +00:00
David Harris
02071700d6 Removed Busybear dependencies 2022-02-02 20:28:21 +00:00
Ross Thompson
6c5b0bec40 More cleanup of IFU. 2022-02-01 14:32:27 -06:00
Ross Thompson
85d510e315 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-01 10:50:38 -06:00
Ross Thompson
73edd50120 Updated fpga's bootloader to reflect the changes to the gpio address change. 2022-02-01 10:43:24 -06:00
Ross Thompson
1f0821da0d IFU and LSU now share the same busdp module. 2022-01-31 16:25:41 -06:00
Ross Thompson
86bac2a083 partial ifu cleanup. 2022-01-31 16:08:53 -06:00
Ross Thompson
e4ee630a3e cleanup. 2022-01-31 13:29:04 -06:00
Ross Thompson
c9a163b8fd Repaired linux-wave.do 2022-01-31 12:54:18 -06:00
Ross Thompson
4422e2f91c Repaired wavefile and fixed modelsim warning. 2022-01-31 12:34:17 -06:00
Ross Thompson
c2b2fae98d Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-01-31 12:17:37 -06:00
Ross Thompson
f4e62bcb54 Cleanup busdp. 2022-01-31 12:17:07 -06:00
Ross Thompson
31da37dd0f Moved lsu virtual memory logic into separate module. 2022-01-31 11:56:03 -06:00
Ross Thompson
9cd502d0af Encapsulated dtim. 2022-01-31 11:23:55 -06:00
Ross Thompson
c939eb20eb Removed unused signals in the LSU. 2022-01-31 10:35:35 -06:00
Ross Thompson
5fe30ff8a9 Moved atomic logic to own module. 2022-01-31 10:28:12 -06:00
Ross Thompson
a4f6653cd8 Encapsulated the bus data path into a separate module. 2022-01-31 10:15:48 -06:00
David Harris
090533cfe9 Replaced || and && with | and & 2022-01-31 01:07:35 +00:00
Ross Thompson
ac50a36aac LSU and IFU cleanup. 2022-01-28 15:26:06 -06:00
Ross Thompson
2e00186eea Updated wave.do to match the ifu/lsu changes. 2022-01-28 14:37:15 -06:00
Ross Thompson
42d60235f0 Clean up of mmu instances in IFU and LSU. 2022-01-28 14:02:05 -06:00
Ross Thompson
c5e0024e9f Moved spills to own module. 2022-01-28 13:40:35 -06:00
Ross Thompson
06209c417f Cleaned up the InstrMisalignedFault. 2022-01-28 13:19:24 -06:00
Ross Thompson
862bf2faae Moved all instr/load/storeamo faults to mmu with the exception of instr misaligned fault. 2022-01-27 17:11:27 -06:00
Ross Thompson
d15cb64bdf Relocated the misalignment faults. 2022-01-27 16:03:00 -06:00
David Harris
30cc27e719 IFU cleanup 2022-01-27 17:18:55 +00:00
David Harris
5ab06fef20 IFU cleanup 2022-01-27 16:41:57 +00:00
David Harris
bdd5796f3a Optimized out second adder from IFU for PC+2 2022-01-27 16:06:24 +00:00
David Harris
7f91170bab Comments in LSU code about restructuring 2022-01-27 15:53:59 +00:00
Ross Thompson
db0a0bd29e BPPredWrongM needs to be 0 when there is no branch predictor. BPPredWRongM is only used when there is an icacheflush. 2022-01-27 07:59:59 -06:00
Ross Thompson
cc5a9a015b Removed mux in PCNextF logic. Minor IFU improvements. 2022-01-26 22:33:26 -06:00
Ross Thompson
42ef1e22e5 1. Modified the cache so it can handle the reset delay internally. This removes the mux from the IFU. 
2. Removed the write address delay from simpleram.sv
3. Fixed rv32tim and rv32ic mode to handle missalignment correctly.
4. Added imperas32i and imperas32c to rv32tim mode.
 2022-01-26 18:23:39 -06:00
Ross Thompson
fc86651937 IFU simplifications. 2022-01-26 13:54:59 -06:00
Ross Thompson
840e814e95 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-01-25 19:21:04 -06:00
David Harris
8d04e83c9f simpleram simplification 2022-01-25 19:46:13 +00:00
David Harris
9da1ed4ed9 simpleram simplification 2022-01-25 19:40:07 +00:00