bbracker
ac114e1c6d
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-02-22 04:27:50 +00:00
bbracker
c26526c9f3
change RX side of UART to aslo be LSB-first
2022-02-22 03:34:08 +00:00
Ross Thompson
1ab2e7590b
Added some clearity to lsuvirtmem.sv.
2022-02-21 17:20:58 -06:00
Ross Thompson
8a280f211f
Annotated IFU for mux changes.
2022-02-21 17:20:34 -06:00
Ross Thompson
ace743ae91
Changed HPTWRead/HPTWWrite to be HPTWRW to be similar to MemRW.
2022-02-21 16:54:38 -06:00
Ross Thompson
414e73edd9
Cleaned up names in lsuvirtmem.
2022-02-21 16:44:30 -06:00
Ross Thompson
456a54166a
Minor cleanup of lsu.
2022-02-21 12:46:06 -06:00
Ross Thompson
5d9ad011d2
Moved mux into lsuvirtmem.
2022-02-21 09:31:29 -06:00
Ross Thompson
8af055c78e
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-21 09:06:09 -06:00
Ross Thompson
a60332b455
Minor changes to LSU.
2022-02-19 14:38:17 -06:00
David Harris
4e194b2576
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-02-18 23:08:47 +00:00
David Harris
a88302f0d7
Removed problematic warning about reaching default state in HPTW
2022-02-18 23:08:40 +00:00
Ross Thompson
0bd533473c
New config option to enable hptw writes to PTE in memory to update Access and Dirty bits.
2022-02-17 17:19:41 -06:00
Ross Thompson
a7b774e453
Accidentally cleared dirty bit when setting access bit in hptw.
2022-02-17 16:20:20 -06:00
Ross Thompson
7dffcba182
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-17 14:49:37 -06:00
Ross Thompson
d152733a17
Rough implementation passing regression test with hptw atomic writes to memory.
2022-02-17 14:46:11 -06:00
David Harris
3036de316a
Started make allsynth to try many experiments
2022-02-17 17:57:02 +00:00
Ross Thompson
4cfb601dc8
Fixed a bunch of the virtual memory changes. Now supports atomic update of PTE in memory concurrent with TLB.
2022-02-17 10:04:18 -06:00
Ross Thompson
565ca4e4a3
Broken state. address translation not working after changes to hptw to support atomic updates to PT.
2022-02-16 23:37:36 -06:00
Ross Thompson
beac362364
Moved a few muxes around after sww changes.
2022-02-16 15:43:03 -06:00
Ross Thompson
6a2bcfcd01
cleanup of signal names.
2022-02-16 15:29:08 -06:00
Ross Thompson
84edb8b5d5
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-16 15:22:35 -06:00
Ross Thompson
bd7343b791
Modified lsu and uncore so only 1 sww is present. The sww is in the LSU if there is a cache or dtim. uncore.sv contains the sww if there is no local memory in the LSU. This is necessary as the subword write needs the read data to be valid and that read data is not aviable in the correct cycle in the LSU if there is no dtim or cache. Muxing could be done to provide the correct read data, but it adds muxes to the critical path.
2022-02-16 15:22:19 -06:00
David Harris
131a1a4ded
Cleaned warning on HPTW default state
2022-02-16 17:40:13 +00:00
David Harris
799736632b
Register file comments about reset
2022-02-16 17:21:05 +00:00
Ross Thompson
a64839d999
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-16 09:48:16 -06:00
David Harris
72e83db9fe
removed csrn and all of its outputs because depricated
2022-02-15 19:59:29 +00:00
David Harris
d3034c4f01
Mostly removed N_SUPPORTED
2022-02-15 19:50:44 +00:00
David Harris
f734afb866
Just needed to recompile - all good. Now removed uretM because N-mode is depricated
2022-02-15 19:48:49 +00:00
David Harris
1326ade1a0
Removed depricated N-mode support and SI/EDELEG registers. rv64gc_wally64priv tests are failing, but seem to be failing before this change.
2022-02-15 19:20:41 +00:00
Ross Thompson
6076f90bbc
Cache mods to be consistant with diagrams.
2022-02-14 12:40:51 -06:00
David Harris
1d5c8a7b98
t push
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-02-14 01:22:22 +00:00
Ross Thompson
1bb4d46ac1
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-13 18:21:15 -06:00
Ross Thompson
e852cb8a31
Eliminated more ports in cacheway.
2022-02-13 15:53:46 -06:00
Ross Thompson
1d7949513d
More cache cleanup.
2022-02-13 15:47:27 -06:00
Ross Thompson
7ffbc6b2ab
Changed names of signals in cache.
2022-02-13 15:06:18 -06:00
Ross Thompson
a5ad4331ec
More cache cleanup.
2022-02-13 12:38:39 -06:00
David Harris
b360e7b941
Synthesis cleanup
2022-02-12 06:25:12 +00:00
David Harris
a34cbdb7d0
Synthesis script cleanup, eliminated privileged instructiosn from controller when ZICSR_SUPPORTED = 0
2022-02-12 05:50:34 +00:00
Ross Thompson
dd944265aa
Formating improvements to cache.
2022-02-11 23:10:58 -06:00
Ross Thompson
bf173b035c
More cache simplifications.
2022-02-11 22:54:05 -06:00
Ross Thompson
16abe90a0d
Reduced seladr to 1 bit as second bit is same as selflush.
2022-02-11 22:41:36 -06:00
Ross Thompson
b11e9eca7b
Reduced complexity of the address selection during flush.
2022-02-11 22:27:27 -06:00
Ross Thompson
1255e82154
Removed redundant signals from cache.
2022-02-11 22:23:47 -06:00
Ross Thompson
52894a7a4f
Cache fsm simplifications.
2022-02-11 15:16:45 -06:00
Ross Thompson
e2e0a4f595
Removed STATE_CPU_BUSY_FINISH_AMO from cache. This is redundant with STATE_CPU_BUSY.
2022-02-11 15:09:00 -06:00
Ross Thompson
0f2ac0cb24
Simplified cache fsm.
2022-02-11 14:54:57 -06:00
Ross Thompson
1c83914662
Fixed bug.
...
It was possible for DTLBMissM to prevent a dcache flush.
2022-02-11 14:00:01 -06:00
Ross Thompson
febd019854
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-11 10:47:21 -06:00
Ross Thompson
6d12010d02
Fixed subtle and infrequenct bug.
...
Loading buildroot at 483M instructions started with a spill + ITLBMiss. The spillsupport logic allowed transition to the second access only after the bus/cache completed the first operation. However the BusStall was suppressed if ITLBMissF occurs resulting in the spillfsm advancing to the second operation. Now the spill logic also takes in ITLBMissF and prevents the early transition to the second access.
2022-02-11 10:46:06 -06:00
