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1225 Commits

Author SHA1 Message Date
Katherine Parry
80f026a734 FMA uses one LOA 2021-12-07 14:15:43 -08:00
bbracker
5a611bd82d undo intentionally breaking commit 2021-12-07 13:43:47 -08:00
bbracker
5d90f899b8 intentionally breaking commit 2021-12-07 13:27:34 -08:00
bbracker
c9808988c1 undo intentionally breaking commit 2021-12-07 13:27:06 -08:00
bbracker
2b41e37160 intentionally breaking commit 2021-12-07 13:23:19 -08:00
Ross Thompson
22721dd923 Added generate around the dtim preload. 
Added readme to explain FPGA.
 2021-12-07 13:12:47 -06:00
Ross Thompson
29743c5e9e Fixed two issues. 
First the xci files already include the xdc constraints for each IP block. There is no need to include the xdc files explicitly.
Second the bidir buffer for the sd card was connected backwards.
 2021-12-07 12:15:50 -06:00
Ross Thompson
c3c9c327b7 Fixed more constraint issues in fpga. 
Added back in the ILA.
Design does not work yet.  Stil having issues with order of automatic
clock and I/O constraint ordering.
Added back in the preload for the boottim.
 2021-12-05 15:14:18 -06:00
Ross Thompson
b03ca464f1 Mostly integrated FPGA flow into main branch. Not all tests passing yet. 2021-12-02 18:00:32 -06:00
Ross Thompson
9ccc8e7f3a Merge branch 'fpga' into main 2021-12-02 14:28:10 -06:00
kwan
5164129172 .* resolved in ifu.sv 2021-12-02 10:32:35 -08:00
kwan
05a838aee2 .* in ifu/ifu.sv eliminated 2021-12-02 09:45:55 -08:00
Ross Thompson
97c73f10ff Fixed uart for FPGA config after merge. This still needs some work. 2021-11-29 16:07:54 -06:00
Ross Thompson
a871118116 Merge branch 'main' into fpga 2021-11-29 10:10:37 -06:00
Ross Thompson
5642918ead Merge branch 'main' into fpga 2021-11-29 10:06:53 -06:00
Noah Limpert
09d3322a26 updated fpu instantion on wallypiplinedhart to remove .*, updated spacing as well 2021-11-24 23:22:04 -08:00
Noah Limpert
93b626ce2a replaced .* instation of priv module on wallypiplinedhart 2021-11-24 22:58:59 -08:00
Noah Limpert
f36cc7a2a3 Made abhlite instation on wallypipehart more clear, updated spacing for consistency 2021-11-24 22:48:01 -08:00
Noah Limpert
5b7c969170 updated module instation of LSU on wallypiplinedhard 2021-11-24 22:09:39 -08:00
Ross Thompson
1183aed049 Missed another change to uart. 2021-11-23 10:20:47 -06:00
Ross Thompson
3fc370654d Fixed syntax error which modelsim did not detect in my changes for making uart work with qemu's simulation. 2021-11-23 10:00:32 -06:00
Ross Thompson
f12e7e1b68 Added QEMU hack for initial LCR value in uart. 2021-11-22 15:23:19 -06:00
Ross Thompson
f05a66acd1 Hack added to uart so QEMU simulation can work with an ultra fast baud rate relative to the clock speed. 2021-11-22 15:20:54 -06:00
Ross Thompson
d5cf6da6eb Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-11-22 11:30:14 -06:00
bbracker
cffb72042a activate STVAL for buildroot 2021-11-21 10:40:28 -08:00
Ross Thompson
e955b17500 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-11-20 22:44:45 -06:00
Ross Thompson
9d3261ed49 Reversed bit order in uart. 2021-11-20 22:43:05 -06:00
Ross Thompson
705572f0ac Fixed a very complex interaction between interrupts, the icache, dcache, and hptw. 
If an interrupt occurred at the start of an ITLB miss or DTLB miss the page table
walk should be aborted before starting.
 2021-11-20 22:35:47 -06:00
slmnemo
0bf1836a3a Removed .* from hazard hzu(.*). 2021-11-17 14:21:23 -08:00
slmnemo
5c28553ca1 Removed .* from hazard hzu(.*) in wallypipelinedhart.sv. 2021-11-17 14:08:08 -08:00
slmnemo
df6c54a664 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-11-17 13:38:51 -08:00
slmnemo
bf8cef78bc removed .* from muldiv.sv (REAL) 2021-11-17 13:37:50 -08:00
Noah Limpert
b63c0f35d1 ieu variable naming changed for clarity 2021-11-17 13:24:28 -08:00
slmnemo
c5c886ddc1 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-11-17 13:23:20 -08:00
slmnemo
40efffc70b Removed .*s from muldiv.sv 2021-11-17 13:23:12 -08:00
Noah Limpert
70a84b56c8 Updated IFU variable naming for clarity 2021-11-17 12:39:05 -08:00
Kip Macsai-Goren
7a8c21e71f renamed presrc to forwardedSrc, replaced SrcAE and SrcBE with Forwarded src in the muldiv 2021-11-17 10:53:17 -08:00
Ross Thompson
f4c221f20a Created separate memory interface for the ddr4 fpga memory from the soc internal memory dtim. 2021-11-17 12:47:19 -06:00
Ross Thompson
23e78c4842 Fixed uart by reversing the bit order on transmit. 
Set prescale to 0.
 2021-11-17 10:32:41 -06:00
Ross Thompson
1c9670d739 Have linux booting. Not sure about uart, but uart is now part of the ILA and I can see TX changing. 2021-11-12 17:37:07 -06:00
Ross Thompson
7497422667 Changed several things. 
Removed the need to use async flip flops in SDC.
Added arrs, a synchronizer for reset.
I think this works with the real FPGA hardware.
The last build did not include this arrs but it worked.
 2021-11-12 11:13:50 -06:00
Kevin
11efaa2669 changed code aligner to run recursively on a root directory 
-only runs the aligner on .sv files
-runs recursively on sub-directories
 2021-11-03 10:49:34 -07:00
David Harris
dda035891a PIPELINE test running 2021-11-01 12:44:35 -07:00
Ross Thompson
9c875d38a9 Fixed the 4 way set associative pseudo LRU replacement policy. 2021-10-29 12:46:02 -05:00
Ross Thompson
41dbb59e24 Possible fix for the incorrect behavior of the pseudo LRU replacement policy for 4 ways set associative caches. 2021-10-29 11:03:37 -05:00
Ross Thompson
35fcadbe7f Applied batch from fpga branch which fixes the dcache fence bug. The should cause the dcache to flush all dirty cache lines to main memory. The bug caused the dirty reset to clear each way for a particular line. 2021-10-28 11:07:18 -05:00
Noah Limpert
27251a9935 Have replaced .* with signal names in ifu 2021-10-27 13:45:37 -07:00
koooo142857
33f5de0f5c aligned all files in ifu folder 2021-10-27 12:43:55 -07:00
David Harris
582c2bf37b Fixed FResultSelM to select proper flags 2021-10-27 11:02:42 -07:00
Ross Thompson
c4170ece27 Replaced async reset flip flops with sync reset flip flops in cache and bpread. 2021-10-27 09:57:11 -05:00
Ross Thompson
400670cb06 Linux now boots fpga. 2021-10-26 16:49:16 -05:00
David Harris
426a43f77b Forgot to save cacheway merge 2021-10-26 08:38:13 -07:00
David Harris
c0145c0a35 merging changes 2021-10-26 08:34:36 -07:00
David Harris
8287a1ef3e Synchronous reset in non-flop blocks 2021-10-26 08:30:35 -07:00
Ross Thompson
c43b19120f Fixed another critical path in the caches. 2021-10-25 22:05:11 -05:00
Ross Thompson
1228dbbebc Fixed the timing issue in the cache replacement polcy. 2021-10-25 18:00:23 -05:00
Ross Thompson
576383c74b Fixed bug with the changes to sram1rw. 2021-10-25 16:11:41 -05:00
Ross Thompson
f0beb4357a Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-10-25 15:36:21 -05:00
Ross Thompson
5fd3f7f2c7 Possible fix for critical path timing in caches. 2021-10-25 15:33:33 -05:00
Ross Thompson
81054d9168 Fixed issue with dtim (fpga) external abhlite select not triggering. 
Setup the bootloader (bios.s) to copy 127MB and blink LEDs for 5 seconds with 1 second period.
 2021-10-25 14:51:54 -05:00
bbracker
39efadf2cf Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-25 12:25:37 -07:00
Ross Thompson
32f0b97cd3 Updated uncore to use sdc. 
Fixed bug with fence instruction not correctly clearing dirty bits in d cache.
 2021-10-25 14:07:44 -05:00
David Harris
fbee4963da Converted flops to synchronous reset now that reset signal is synchronized 2021-10-25 11:49:20 -07:00
David Harris
2bf51362e2 Added synchronizer to reset 2021-10-25 10:05:41 -07:00
Ross Thompson
76bba541a7 Modified the cache's sram model so if it used to synthesize flip flops it terminates the read critical path at the address's input rather than the output read data. 2021-10-24 21:21:49 -05:00
bbracker
046a78a8fc manually resolved git merge conflicts in testbench linux after checkpointing 2021-10-24 15:02:19 -07:00
Ross Thompson
8a51fe76c1 Partial cleanup of unused signals in caches and bpred. 2021-10-24 15:04:20 -05:00
bbracker
36b39358c6 add checkpointing to linux testbench 2021-10-24 06:47:35 -07:00
David Harris
c9e9cd4a60 more lsu/ifu lint cleanup 2021-10-23 12:10:13 -07:00
David Harris
2cfbd888fd more lsu/ifu lint cleanup 2021-10-23 12:00:32 -07:00
David Harris
62a23fe878 lsu/ifu lint cleanup 2021-10-23 11:41:20 -07:00
David Harris
61fdb3d902 random lint cleanup 2021-10-23 11:24:36 -07:00
David Harris
8d9efcbafb IEU cleanup 2021-10-23 11:13:28 -07:00
David Harris
4bf823e063 lint cleanup 2021-10-23 11:03:28 -07:00
David Harris
d570df864f IEU lint cleanup 2021-10-23 10:51:53 -07:00
David Harris
8e516e6391 Lint cleanup from wallypipeliendhart 2021-10-23 10:29:52 -07:00
David Harris
33358d101e Lint cleanup: ahblite, ifu, hart 2021-10-23 10:12:33 -07:00
David Harris
d24bece3a8 Lint cleanup 2021-10-23 09:58:52 -07:00
David Harris
2e796e3da2 lint cleanup: FPU and privileged 2021-10-23 09:41:24 -07:00
David Harris
c316bff15a subword read and csrc lint cleanup 2021-10-23 09:29:15 -07:00
David Harris
28d8f6d5cf FMA and CSRC lint cleanup 2021-10-23 09:20:24 -07:00
David Harris
11b0607e63 Lint cleanup 2021-10-23 09:06:21 -07:00
David Harris
ac1b1bfbb6 update scripts for handling src/*/* subdirectories 2021-10-23 08:54:29 -07:00
David Harris
0dabb6ebd4 lint cleaning and moved files into subdirectories 2021-10-23 08:53:32 -07:00
David Harris
f483e8002a Lint cleanup 2021-10-23 08:39:21 -07:00
David Harris
e2e950ac0f Cleaned up LINT erors 2021-10-23 06:28:49 -07:00
David Harris
4c480a40f6 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-23 06:15:49 -07:00
David Harris
3249d65209 Added -lint flag to vsim. Cleaned some lint errors. Moved lint-wally to regression directory for convenience. 2021-10-23 06:15:26 -07:00
Ross Thompson
77e2b6f9a9 Merge branch 'main' into fpga 2021-10-22 16:09:16 -05:00
James E. Stine
f6e8e45901 Modify register before fpdivsqrt to be synthesizable for FPGAs and better in tune for ASIC clocking 2021-10-22 13:41:50 -05:00
Katherine Parry
7c7c0f538a put the FMA priority encoders into their own module 2021-10-22 10:03:12 -07:00
James E. Stine
0dcca43f48 Get rid of lint warning - still need more testing though 2021-10-21 15:19:22 -05:00
James E. Stine
dd7dbaa382 Clean up some FPU and add pipelined fpdivsqrt to fpu.sv 2021-10-21 13:52:12 -05:00
James E. Stine
bafb3a983d Fix fpdivsqrt lint error on CPA for convergence 2021-10-20 17:46:13 -05:00
Ross Thompson
de4ea16d32 Merge branch 'main' into fpga 2021-10-20 16:24:55 -05:00
Ross Thompson
fe24bc5a43 Added debug signals to dcache. 2021-10-20 15:52:05 -05:00
David Harris
ceaf84a3ce removed .* from wallypipeliendsoc 2021-10-20 13:49:18 -07:00
James E. Stine
71b48048da Added pipelined version of fpdivsqrt as well as analysis of fpdivsqrt to cut multiplier down to 60bits. 2021-10-20 12:00:41 -05:00
James E. Stine
41010aa418 Some more sanitization but will pass to legal to determine if okay on version - it is substantially different in some ways but not a legal expert on this 2021-10-19 12:09:43 -05:00
James E. Stine
a75abb04bd Modify DW02_multp to properly list the correct number of bits at the output (i.e., 2*WIDTH + 2). 2021-10-19 11:58:06 -05:00
Ross Thompson
d11136c406 Fixed bug with the external memory region selection. 
Updated bios program to copy just 127MB to dram.
 2021-10-19 11:23:23 -05:00
David Harris
3bc985d230 Changed some flops to settable 2021-10-18 17:05:29 -07:00
David Harris
0516ee768b replaced flopenl with flopenr when clearing to 0 2021-10-18 16:53:18 -07:00
David Harris
398337951d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-18 15:44:31 -07:00
David Harris
00d8035836 Fixed multiplier and pointed arch tests to new path in addins 2021-10-18 15:43:59 -07:00
Ross Thompson
cd58a388e4 fixed issues with dc shell not liking modules with parameters without default values. 2021-10-18 17:24:15 -05:00
James E. Stine
37fe5e56a8 Sanitization some more on mult_cs.sv 2021-10-18 05:24:16 -05:00
James E. Stine
d0ab43e4e8 Update some on mult_cs and delete DW02_mult.v 2021-10-18 05:06:49 -05:00
James E. Stine
de7b673e34 Add hacky hand-made carry/save multiplier - will improve 2021-10-16 10:37:29 -05:00
Katherine Parry
c34633804a cvtfp module documented 2021-10-14 15:25:31 -07:00
James E. Stine
c5b99300e7 Clean up some signals - beautification onging 2021-10-14 17:12:00 -05:00
Skylar Litz
71397d5db9 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-10-13 15:38:32 -07:00
Skylar Litz
4ca4e13ba2 add StallM signal back to DivStartE control 2021-10-13 15:34:40 -07:00
James E. Stine
1dba57dce7 Update to fpdivsqrt to go on posedge as it should. Also an update to 
individual regression test for TestFloat (still needs some tweaking)
 2021-10-13 17:14:42 -05:00
Katherine Parry
b79021a73e lint warnings fixed 2021-10-12 09:45:02 -07:00
Katherine Parry
539d21645f some fpu lint warnings fixed - still working on it 2021-10-11 18:32:03 -07:00
Ross Thompson
f6c6cb9ed2 Merge branch 'main' into fpga 2021-10-11 18:17:58 -05:00
Ross Thompson
b3694bfdfd Fixed boot loader program to start at correct address. 
modified script which converts the ram.txt into preload text file for sdc simulation.
created script to convert ram.txt into binary to write to flash card.
added top level for solo sd card fpga.
 2021-10-11 17:22:23 -05:00
Shreya Sanghai
0acf9fd746 made redunantmul generate DW02_multp for synopsys sythnesis 2021-10-11 11:54:39 -07:00
Shreya Sanghai
84ff2b49c7 actually added redundant mul 2021-10-11 11:29:13 -07:00
Shreya Sanghai
a1c9ffdf2b added redundant multiplier 2021-10-11 11:20:12 -07:00
David Harris
ab6a796690 Starting to optimize multiplier 2021-10-11 11:06:07 -07:00
Ross Thompson
f1eda1bf6f Fixed sdc byte and nibble orders. 2021-10-11 12:15:52 -05:00
Ross Thompson
bfe633d087 Partially working sd card reader. 2021-10-11 10:23:45 -05:00
David Harris
f1190b6ceb intdiv cleanup 2021-10-11 08:14:21 -07:00
David Harris
4139f27d10 Divider FSM simplification 2021-10-10 22:24:14 -07:00
David Harris
75c17dc372 Major reorganization of regression and simulation and testbenches 2021-10-10 15:07:51 -07:00
David Harris
a6c6b2b974 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-10 12:26:15 -07:00
David Harris
caf3c2de9b Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-10 12:25:11 -07:00
bbracker
90ccd60790 simplify flopenrc's that didn't actually need to be flopenrc's 2021-10-10 12:25:05 -07:00
David Harris
43d92f2507 Divider cleanup 2021-10-10 12:24:44 -07:00
David Harris
6704e37597 Simplifying divider FSM 2021-10-10 12:21:43 -07:00
David Harris
4deae8019a Simplifying divider FSM 2021-10-10 12:21:36 -07:00
David Harris
2759f1fcb1 Moved & ~StallM from FSM into DivStartE 2021-10-10 11:49:32 -07:00
David Harris
635fe181f8 Moved divide iteration register names to M stage 2021-10-10 11:30:53 -07:00
David Harris
b713b6ca87 Simplified remainder for divide by 0 2021-10-10 11:20:07 -07:00
David Harris
6988c8c37c divider control signal simplificaiton 2021-10-10 10:55:02 -07:00
David Harris
c2bb0324c6 Removed negedge flops from divider 2021-10-10 10:41:13 -07:00
David Harris
3aa9e088c8 Simplified divider sign handling 2021-10-10 08:35:26 -07:00
David Harris
39bbeefa78 renamed DivStart 2021-10-10 08:32:04 -07:00
David Harris
64ed267825 renamed DivSigned 2021-10-10 08:30:19 -07:00
Katherine Parry
77fe00947e FMA matches diagram and lint warnings fixed 2021-10-09 17:38:10 -07:00
kipmacsaigoren
96565f9435 rename adder in fpu for synthesis 2021-10-08 17:47:54 -05:00
kipmacsaigoren
7fde7aae6e Merging new changes into the old one's I've made in the OKstate servers 2021-10-08 17:47:11 -05:00
Kip Macsai-Goren
f3058f94c6 removed loops and simplified mask generation logic. PMP's now pass my tests and linux tests up to around 300M instructions. 2021-10-08 15:33:18 -07:00
kipmacsaigoren
2d4623b49c Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-10-08 12:01:44 -05:00
bbracker
1824b2af13 fix div restarting bug 2021-10-07 18:55:00 -04:00
kipmacsaigoren
8db7ce002d Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-10-06 11:52:34 -05:00
James E. Stine
a91c0c8fc7 Make changes to fpdiv - still working on clock issue with fsm that was changed from posedge to negedge - also updated fpdivsqrt rounding to handle testfloat 2021-10-06 08:26:09 -05:00
kipmacsaigoren
b72e94badf Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-10-04 12:28:03 -05:00