forked from Github_Repos/cvw
replaced .* instation of priv module on wallypiplinedhart
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@ -293,7 +293,7 @@ module wallypipelinedhart (
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muldiv mdu(
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.clk, .reset,
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.clk, .reset,
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// Execute Stage interface
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// .SrcAE, .SrcBE,
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.ForwardedSrcAE, .ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B
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@ -321,7 +321,37 @@ module wallypipelinedhart (
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); // global stall and flush control
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// Priveleged block operates in M and W stages, handling CSRs and exceptions
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privileged priv(.*);
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privileged priv(
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.clk, .reset,
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.FlushD, .FlushE, .FlushM, .FlushW,
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.StallD, .StallE, .StallM, .StallW,
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.CSRReadM, .CSRWriteM, .SrcAM, .PCM,
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.InstrM, .CSRReadValW, .PrivilegedNextPCM,
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.RetM, .TrapM,
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.ITLBFlushF, .DTLBFlushM,
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.InstrValidM, .CommittedM,
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.FRegWriteM, .LoadStallD,
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.BPPredDirWrongM, .BTBPredPCWrongM,
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.RASPredPCWrongM, .BPPredClassNonCFIWrongM,
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.InstrClassM, .DCacheMiss, .DCacheAccess, .PrivilegedM,
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.ITLBInstrPageFaultF, .DTLBLoadPageFaultM, .DTLBStorePageFaultM,
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.WalkerInstrPageFaultF, .WalkerLoadPageFaultM, .WalkerStorePageFaultM,
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.InstrMisalignedFaultM, .IllegalIEUInstrFaultD, .IllegalFPUInstrD,
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.LoadMisalignedFaultM, .StoreMisalignedFaultM,
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.TimerIntM, .ExtIntM, .SwIntM,
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.MTIME_CLINT, .MTIMECMP_CLINT,
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.InstrMisalignedAdrM, .MemAdrM,
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.SetFflagsM,
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// Trap signals from pmp/pma in mmu
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// *** do these need to be split up into one for dmem and one for ifu?
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// instead, could we only care about the instr and F pins that come from ifu and only care about the load/store and m pins that come from dmem?
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.InstrAccessFaultF, .LoadAccessFaultM, .StoreAccessFaultM,
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.ExceptionM, .PendingInterruptM, .IllegalFPUInstrE,
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.PrivilegeModeW, .SATP_REGW,
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.STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP,
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.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
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.FRM_REGW,.BreakpointFaultM, .EcallFaultM
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);
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fpu fpu(.*); // floating point unit
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