forked from Github_Repos/cvw
Updated IFU variable naming for clarity
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@ -155,26 +155,41 @@ module wallypipelinedhart (
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ifu ifu(
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.clk, .reset,
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.StallF, .StallD, .StallE, .StallM, .StallW,
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.FlushF, .FlushD, .FlushE, .FlushM, .FlushW,
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.InstrInF(InstrRData), .InstrAckF, .PCF, .InstrPAdrF, .InstrReadF, .ICacheStallF,
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.clk, .reset,
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.StallF, .StallD, .StallE, .StallM, .StallW,
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.FlushF, .FlushD, .FlushE, .FlushM, .FlushW,
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// Fetch
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.InstrInF(InstrRData), .InstrAckF, .PCF, .InstrPAdrF,
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.InstrReadF, .ICacheStallF,
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// Execute
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.PCLinkE, .PCSrcE, .PCTargetE, .PCE,
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.BPPredWrongE,
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.RetM, .TrapM,
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.PrivilegedNextPCM, .InvalidateICacheM,
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.InstrD, .InstrM,
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.PCM, .InstrClassM,
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.BPPredDirWrongM,.BTBPredPCWrongM,.RASPredPCWrongM, .BPPredClassNonCFIWrongM,
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.IllegalBaseInstrFaultD, .ITLBInstrPageFaultF, .IllegalIEUInstrFaultD,
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.InstrMisalignedFaultM, .InstrMisalignedAdrM,
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// Mem
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.RetM, .TrapM, .PrivilegedNextPCM, .InvalidateICacheM,
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.InstrD, .InstrM, . PCM, .InstrClassM, .BPPredDirWrongM,
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.BTBPredPCWrongM, .RASPredPCWrongM, .BPPredClassNonCFIWrongM,
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// Writeback
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// output logic
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// Faults
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.IllegalBaseInstrFaultD, .ITLBInstrPageFaultF,
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.IllegalIEUInstrFaultD, .InstrMisalignedFaultM,
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.InstrMisalignedAdrM,
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// mmu management
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.PrivilegeModeW, .PTE, .PageType, .SATP_REGW,
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.STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP,
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.ITLBWriteF, .ITLBFlushF,
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.WalkerInstrPageFaultF,
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.ITLBMissF,
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.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
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.STATUS_MXR, .STATUS_SUM, .STATUS_MPRV,
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.STATUS_MPP, .ITLBWriteF, .ITLBFlushF,
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.WalkerInstrPageFaultF, .ITLBMissF,
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// pmp/pma (inside mmu) signals. *** temporarily from AHB bus but eventually replace with internal versions pre H
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.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
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.InstrAccessFaultF
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); // instruction fetch unit: PC, branch prediction, instruction cache
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