Noah Limpert 93b626ce2a replaced .* instation of priv module on wallypiplinedhart		2021-11-24 22:58:59 -08:00
..
cache	Fixed a very complex interaction between interrupts, the icache, dcache, and hptw.	2021-11-20 22:35:47 -06:00
ebu
fpu	PIPELINE test running	2021-11-01 12:44:35 -07:00
generic	Converted flops to synchronous reset now that reset signal is synchronized	2021-10-25 11:49:20 -07:00
hazard
ieu	renamed presrc to forwardedSrc, replaced SrcAE and SrcBE with Forwarded src in the muldiv	2021-11-17 10:53:17 -08:00
ifu	Fixed a very complex interaction between interrupts, the icache, dcache, and hptw.	2021-11-20 22:35:47 -06:00
lsu	Fixed a very complex interaction between interrupts, the icache, dcache, and hptw.	2021-11-20 22:35:47 -06:00
mmu	more lsu/ifu lint cleanup	2021-10-23 12:10:13 -07:00
muldiv	Removed .* from hazard hzu(.*) in wallypipelinedhart.sv.	2021-11-17 14:08:08 -08:00
privileged	activate STVAL for buildroot	2021-11-21 10:40:28 -08:00
uncore	Missed another change to uart.	2021-11-23 10:20:47 -06:00
wally	replaced .* instation of priv module on wallypiplinedhart	2021-11-24 22:58:59 -08:00