Ross Thompson
|
9ebea891e2
|
More cachefsm cache flush cleanup.
|
2022-12-16 16:32:21 -06:00 |
|
Ross Thompson
|
731fbfc851
|
Oups found a bug with the new flush cache states.
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2022-12-16 16:22:40 -06:00 |
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Ross Thompson
|
41c636ecfa
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally
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2022-12-16 15:37:03 -06:00 |
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Ross Thompson
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b462554896
|
Cleanup of cache flush fsm enhancement.
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2022-12-16 15:36:53 -06:00 |
|
Ross Thompson
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dacba855da
|
Rough draft of cache flush fsm enhancement.
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2022-12-16 15:28:22 -06:00 |
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cturek
|
4b8cbd9fa0
|
Added integer support for initC
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2022-12-16 19:02:11 +00:00 |
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Ross Thompson
|
bc907f3e2f
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally
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2022-12-16 12:52:22 -06:00 |
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Ross Thompson
|
e425ecac96
|
Fixed regression-wally to correct remove and mkdir wkdir.
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2022-12-16 12:51:21 -06:00 |
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cturek
|
06c58f310d
|
Added mux for integer special case, renamed signals to match pipelined stage
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2022-12-16 18:43:49 +00:00 |
|
David Harris
|
378c40002f
|
Clean up interrupt masking by Commit
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2022-12-16 08:27:39 -08:00 |
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David Harris
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7989f449ad
|
Disabled starting FPU divider when IDIV_ON_FPU = 0
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2022-12-16 06:35:29 -08:00 |
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cturek
|
d7571bb9b1
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-12-16 03:41:39 +00:00 |
|
David Harris
|
b7abc0037e
|
Use FlushE to reset integer divider FSM
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2022-12-15 11:00:54 -08:00 |
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David Harris
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4365c99b52
|
Refactored stalls and flushes, including FDIV flush with FlushE
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2022-12-15 10:56:18 -08:00 |
|
David Harris
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5b040b7935
|
Regression delete wkdir files to prevent spurious failures
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2022-12-15 10:24:58 -08:00 |
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David Harris
|
2457448e29
|
Renamed DIV_BITSPERCYCLE to IDIV_BITSPERCYCLE
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2022-12-15 08:23:34 -08:00 |
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Ross Thompson
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fa19a111c6
|
Hazard cleanup.
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2022-12-15 10:05:17 -06:00 |
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Ross Thompson
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e774dd2db9
|
Reworked the hazards to eliminate StallFCause. Flush and CSRWrites now flush F,D,E stages and set the correct PCNextF in the M stage.
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2022-12-15 09:53:35 -06:00 |
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Ross Thompson
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b02550b05c
|
Merge branch 'main' into hazards
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2022-12-15 08:44:59 -06:00 |
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David Harris
|
33aca5d35e
|
Added IDIV_ON_FPU flag to control whether integer division uses FPU
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2022-12-15 06:37:55 -08:00 |
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David Harris
|
5f637ef4a7
|
Use FPU divider for integer division when F is supported
|
2022-12-14 17:03:13 -08:00 |
|
cturek
|
8829e627eb
|
Fixed BZero and initU/initUM muxes
|
2022-12-14 16:44:46 +00:00 |
|
Ross Thompson
|
09dcb56217
|
Signal renames to reflect figures.
|
2022-12-14 09:49:15 -06:00 |
|
Ross Thompson
|
a3ec829b80
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-12-14 09:34:34 -06:00 |
|
Ross Thompson
|
6da7849d27
|
Reduced complexity of linebytemask.
|
2022-12-14 09:34:29 -06:00 |
|
cturek
|
ed59736a4b
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
|
2022-12-14 15:13:44 +00:00 |
|
Ross Thompson
|
1ba1bed0b0
|
Broken dont' use.
|
2022-12-11 23:24:01 -06:00 |
|
Ross Thompson
|
0716aedbd5
|
Removed unused flushf.
|
2022-12-11 16:28:11 -06:00 |
|
Ross Thompson
|
115e9e7bb3
|
Renamed CPUBusy to GatedStallF in IFU.
|
2022-12-11 15:54:19 -06:00 |
|
Ross Thompson
|
ffc5bce0b6
|
Renamed CPUBusy in LSU.
|
2022-12-11 15:52:51 -06:00 |
|
Ross Thompson
|
c50a2bd8bf
|
Changed CPUBusy to Stall in ebu modules.
|
2022-12-11 15:51:35 -06:00 |
|
Ross Thompson
|
3ddf509f28
|
Renamed CPUBusy to Stall in cache.
|
2022-12-11 15:49:34 -06:00 |
|
Ross Thompson
|
4aadd87679
|
Moved CPUBusy out of HPTW.
|
2022-12-11 15:48:00 -06:00 |
|
cturek
|
f57211bb49
|
Fixed D sizing issues across fdivsqrt. Fixed preproc to accept either int or float inputs
|
2022-12-10 21:56:35 +00:00 |
|
Ross Thompson
|
d15cf5c65c
|
Added comments about why it is not possible to use FlushWay and VictimWay directly.
|
2022-12-09 17:07:35 -06:00 |
|
Ross Thompson
|
1463e9b1d4
|
Finished merge of kip and ross's ifu fix.
|
2022-12-09 16:52:22 -06:00 |
|
Ross Thompson
|
6f01ea12e8
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-12-09 16:42:16 -06:00 |
|
Ross Thompson
|
38adcb5b17
|
Minor simplification of cacheway way selection muxes.
|
2022-12-09 16:42:05 -06:00 |
|
Kip Macsai-Goren
|
f486a763d9
|
Addded fix for 32 bit periph test and added test to regression
|
2022-12-06 09:56:08 -08:00 |
|
Ross Thompson
|
033f844d09
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-12-06 10:38:14 -06:00 |
|
Ross Thompson
|
9ee2d84c7c
|
Fixed bug Kip found.
The no cache and no bus versions lacked assignment of CacheCommittedF in the IFU.
|
2022-12-06 10:37:45 -06:00 |
|
Kip Macsai-Goren
|
2dfa426e10
|
added passing GPIO test to 64 bit tests
|
2022-12-05 21:31:00 -08:00 |
|
Kip Macsai-Goren
|
c6c0ef05db
|
commented out periph test from wally32 periph so rv32ic doesn't hang
|
2022-12-05 20:23:16 -08:00 |
|
Kip Macsai-Goren
|
ae32e2a9ee
|
added passing tests to regression
|
2022-12-05 20:16:02 -08:00 |
|
Kip Macsai-Goren
|
282d06b45f
|
added -01 to all WALLY tests
|
2022-12-05 20:16:02 -08:00 |
|
Ross Thompson
|
9806babe9e
|
Renamed SelBusBuffer to SelFetchBuffer.
|
2022-12-05 17:51:13 -06:00 |
|
Ross Thompson
|
0fdbfb87eb
|
Removed commented code.
|
2022-12-05 17:21:56 -06:00 |
|
Ross Thompson
|
bcb927d172
|
Renamed VictimTag to just Tag. Tag is used for both the victim and flush tags.
|
2022-12-05 17:19:51 -06:00 |
|
Ross Thompson
|
2bcaacb179
|
Cache signal renames.
|
2022-12-04 16:09:09 -06:00 |
|
Ross Thompson
|
b84b709182
|
Optimized way selection logic.
|
2022-12-04 12:30:56 -06:00 |
|
Ross Thompson
|
74d5ccc2b1
|
Found possible optimization as the way selection is shared in cache, cacheway, and cachelru.
|
2022-12-04 01:20:51 -06:00 |
|
Ross Thompson
|
62e495c739
|
Moved selectedway mux into cacheway. It makes way more sense there.
|
2022-12-04 01:15:47 -06:00 |
|
Ross Thompson
|
e1ac736d43
|
Rename LineByteMux to FetchbufferbyteSel.
|
2022-12-04 01:00:04 -06:00 |
|
Ross Thompson
|
128b3d20e7
|
Updated riscv arch test removed misaligned1.
|
2022-12-04 00:18:10 +00:00 |
|
Ross Thompson
|
de99663b97
|
Revert "Changed weird D sizing. Better names in preproc. Finalized Int/Float input to divider."
This reverts commit 70b89e5214.
|
2022-12-04 00:01:58 +00:00 |
|
cturek
|
70b89e5214
|
Changed weird D sizing. Better names in preproc. Finalized Int/Float input to divider.
|
2022-12-02 21:44:29 +00:00 |
|
cturek
|
1f32603c30
|
Added flops to preproc
|
2022-12-02 20:31:08 +00:00 |
|
David Harris
|
9395414df3
|
Renamed FPUStallD to FCvtIntStallD
|
2022-12-02 11:55:23 -08:00 |
|
David Harris
|
d64cd715f9
|
Renamed DivStartE to IFDivStartE
|
2022-12-02 11:30:49 -08:00 |
|
David Harris
|
9c1b7e53e4
|
FPU divider working with execute stage stall
|
2022-12-02 11:11:53 -08:00 |
|
David Harris
|
01028e7088
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-12-02 04:28:50 -08:00 |
|
David Harris
|
4c6003d9e2
|
update test list
|
2022-12-02 04:28:47 -08:00 |
|
Ross Thompson
|
33e4361de5
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-12-01 22:36:07 -06:00 |
|
David Harris
|
8afc054e74
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-12-01 16:27:36 -08:00 |
|
David Harris
|
ed39099405
|
reorder tests
|
2022-12-01 16:27:33 -08:00 |
|
Ross Thompson
|
1d9b5badee
|
Properly flush cacheLRU.
|
2022-12-01 17:32:58 -06:00 |
|
David Harris
|
f64c0589fe
|
FPU test list
|
2022-12-01 10:18:36 -08:00 |
|
Ross Thompson
|
da92cdccd0
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-12-01 11:47:54 -06:00 |
|
Ross Thompson
|
cb310bfb1d
|
Removed unused port on cacheway.
|
2022-12-01 11:47:48 -06:00 |
|
David Harris
|
558f0b655e
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-12-01 08:15:51 -08:00 |
|
David Harris
|
4e5f62a5c1
|
code cleanup
|
2022-12-01 08:15:48 -08:00 |
|
Ross Thompson
|
b0b16acaf5
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-11-30 17:19:04 -06:00 |
|
David Harris
|
aa26a97b36
|
signal sufixes in integer division
|
2022-11-30 15:15:37 -08:00 |
|
Ross Thompson
|
f9ffcf377b
|
Reverted the IROM/DTIM address range modelsim assignment.
|
2022-11-30 17:13:33 -06:00 |
|
Ross Thompson
|
bfd238a4fc
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-11-30 13:30:37 -06:00 |
|
Ross Thompson
|
813b2963fb
|
More optimization.
|
2022-11-30 11:26:48 -06:00 |
|
Ross Thompson
|
da7b13ba0a
|
Removed reset on dirty cache bits.
|
2022-11-30 11:04:37 -06:00 |
|
Ross Thompson
|
5e5cca6ae1
|
Turns out the merge of dirty and tag bits is complicated by the need to have byte write enables rather than bit write enables. Putting on hold for now.
|
2022-11-30 11:01:25 -06:00 |
|
Ross Thompson
|
ac3e02692b
|
Preparing to merge dirty and tag srams.
|
2022-11-30 10:40:48 -06:00 |
|
Ross Thompson
|
8692ccbafb
|
Intermediate commit. Replaced flip flop dirty bit array with sram.
|
2022-11-30 00:08:31 -06:00 |
|
cturek
|
e28a6901a9
|
div tests in sim-wally
|
2022-11-30 02:32:04 +00:00 |
|
Ross Thompson
|
e3577781b0
|
Optimization of cacheway.
|
2022-11-29 18:30:47 -06:00 |
|
Ross Thompson
|
1e2180ef98
|
Updated HPTW to route access faults generated by the HPTW to the original access type either instruction access fault, load access fault or store access fault.
|
2022-11-29 17:19:31 -06:00 |
|
Ross Thompson
|
5e550fe5e6
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-11-29 14:57:38 -06:00 |
|
Ross Thompson
|
9e4166407b
|
Fixed a bug with the replacement policy. It was updating the wrong set on load hits.
|
2022-11-29 14:51:09 -06:00 |
|
Ross Thompson
|
179d321683
|
Cleaned up the wavefile and added logic to linearly populate the LRU before all ways are filled.
|
2022-11-29 14:09:48 -06:00 |
|
Kip Macsai-Goren
|
66fcb2bffe
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-11-29 10:43:44 -08:00 |
|
Kip Macsai-Goren
|
26b4147f40
|
added failing satp invalid tests to regression
|
2022-11-29 10:43:38 -08:00 |
|
Ross Thompson
|
ed54959378
|
Renamed signals in the cache.
|
2022-11-29 10:52:40 -06:00 |
|
Ross Thompson
|
4e52755c9f
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-11-22 18:07:32 -06:00 |
|
cturek
|
7140642c93
|
Almost done with Int division
|
2022-11-22 22:22:59 +00:00 |
|
cturek
|
3fbccbf119
|
Updated testbench/wave for fdivsqrt new start signals
|
2022-11-22 22:22:26 +00:00 |
|
Ross Thompson
|
1736983557
|
Cleanup cacheLRU.
|
2022-11-22 14:59:01 -06:00 |
|
Ross Thompson
|
2ae7b555be
|
File name change for cachereplacement policy to cacheLRU
|
2022-11-20 22:35:02 -06:00 |
|
Ross Thompson
|
84679c0062
|
Signal name changes for LRU.
|
2022-11-20 22:31:36 -06:00 |
|
Ross Thompson
|
736a30afac
|
Missing a file. Last commit will fail.
|
2022-11-17 17:45:41 -06:00 |
|
Ross Thompson
|
a1f39a8186
|
Finally have the correct replacement policy implementation.
|
2022-11-17 17:36:37 -06:00 |
|
Ross Thompson
|
ac0f6ddb7b
|
I found the issue with the cache changes. FlushW is not asserted for all TrapM. Ecall and Ebreak don't flush the W stage. However the ifu's bus controllable must disable the BusRW for all traps.
|
2022-11-16 15:38:37 -06:00 |
|
Ross Thompson
|
9b2236b2a0
|
Progress on the cache replacement policy implementation.
|
2022-11-16 15:35:34 -06:00 |
|
Ross Thompson
|
cf964e30fb
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-11-16 12:42:29 -06:00 |
|