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670 Commits

Author SHA1 Message Date
David Harris
ba7e017bd9 Added Zcb c.lbu coverage test 2024-01-10 10:01:46 -08:00
David Harris
d36b6e919a Fixed missing Zba ISA string from spike_rv64gc_isa.yaml for RISCOF 2024-01-09 10:00:06 -08:00
David Harris
caedab679a Rewrote testbench to count signature entries rather than looking for x; this will facilitate Verilator which does not use x 2024-01-07 07:14:12 -08:00
David Harris
0781cd4a44 Improved tlbcontrol to fault on R=0,W=1; fixed more coverage testsin tlbmisc.S; changed integer type to try to speed up CoreMark; comments in Verilate 2024-01-05 22:45:15 -08:00
David Harris
ed623f1a71 Fixed unsupported riscof YAML string; preparing for Verilator -G testcase 2024-01-05 20:06:21 -08:00
David Harris
680a014876 Finished LSU tlbcontrol coverage tests 2024-01-02 10:16:20 -08:00
David Harris
d229dc06ee Coverage improvements; remove incorrect logic checking NAPOT nonleaf PTE 2024-01-02 00:35:17 -08:00
David Harris
52b6d1d163 restored tlbNAPOT coverage tests 2023-12-31 09:55:58 -08:00
David Harris
b025cd8a0d Updated tlbNAPOT to test instructions as well 2023-12-20 23:01:35 -08:00
David Harris
9ced88c55c Fixed tlbNAPOT test to run and makefile to gather coverage stats 2023-12-20 21:45:14 -08:00
David Harris
d130a78616 Updated to current version of toolchain and prepare to be able to compile Zcb and Zicboz when supported 2023-12-20 16:29:03 -08:00
David Harris
0ff049db86 Removed unused tests from wally-riscv-arch-test 2023-12-20 13:34:12 -08:00
David Harris
8552369687 Merged PR538, delete unused tests 2023-12-20 13:30:31 -08:00
Rose Thompson
70d0169019 All regression tests which matter are running! 2023-12-20 14:57:52 -06:00
Rose Thompson
1b59182d59 Updated tests with ending label. 2023-12-20 14:55:37 -06:00
Rose Thompson
49b1b7c7f9 Fixed the last uninitialized memory issue in the priv tests. 2023-12-19 16:51:56 -06:00
Rose Thompson
b04ad23c33 Fixed bugs in the wally64periph signature. 2023-12-19 16:16:59 -06:00
Rose Thompson
726efee1e2 Fixed bugs in the cbom test. 2023-12-19 15:53:48 -06:00
Rose Thompson
418ae0decc Fixed some regression tests with David's help. 2023-12-19 14:18:21 -06:00
David Harris
a138ef37b1 Switched to using riscv-arch-test rv32e_m suite. Need to rename it from rv32e_unratified (PR pending) 2023-12-15 19:26:50 -08:00
David Harris
38f4d9baf8 Use riscv-arch-test arch32e instead of outdated wally-riscv-arch-test wally32e 2023-12-15 05:05:53 -08:00
David Harris
29f57958a9 Fixed WALLY-lrsc in ImperasDV by setting reservation set size to native word size and adjusting imperas.ic lr_sc_grain=8 to match 2023-12-14 15:32:36 -08:00
David Harris
166c98b6f6 Fixed issue 526 about WALLY-mmu-sv39-svadu-svnapot-svpbmt not checking ppn for NAPOT pages. Improved test case to check normal and malformed ppn 2023-12-13 19:43:17 -08:00
David Harris
6c017141c5 Renamed HADE to ADUE for Svadu 2023-12-13 11:49:04 -08:00
David Harris
0f0b4b0c1c Added make wally-riscv-arch-test to tests/riscof to only build custom tests 2023-12-06 07:19:12 -08:00
David Harris
2b2016271a repo cleanup and start to add CMO tests 2023-11-20 23:41:36 -08:00
Rose Thompson
540d8d930d Cleanup. 
Linux makefile
wally tracer.  probably reduce some complexity here.
 2023-11-13 14:04:43 -06:00
Rose Thompson
9dfe421c55 Yay! Zicclsm passes my regression test now. 2023-11-10 18:28:51 -06:00
Rose Thompson
c0e02ae190 Found another bug in the RTL's Zicclsm alignment. 2023-11-10 18:26:55 -06:00
Rose Thompson
02ab9fe99c Fixed all the bugs associated with the signature and the store side of misaligned access. Load misaligned is still causing some issues. 2023-11-10 17:58:42 -06:00
Rose Thompson
bd866e1025 Fixed some more bugs in the Zicclsm signature. 2023-11-10 17:36:10 -06:00
Rose Thompson
efecb0c346 Fixed bug in the Zicclsm test. 2023-11-10 17:34:23 -06:00
Rose Thompson
ada354f443 Fixed bug in the misaligned access test. 2023-11-10 17:02:15 -06:00
Rose Thompson
b74bfbeefd Merge branch 'main' into Zicclsm 2023-11-10 16:15:32 -06:00
naichewa
d67badfc60 fix hardware interlock, hold mode deassert 2023-11-08 15:20:51 -08:00
naichewa
a5837eb62c fifo fixes and edge case testing 2023-11-07 17:59:46 -08:00
naichewa
4651b807ed added test cases 2023-11-02 15:43:08 -07:00
Rose Thompson
0a4ed5515b Merge branch 'main' into Zicclsm 2023-11-02 12:55:51 -05:00
Rose Thompson
afa1d85e3b Doesn't yet fully work. 
Thomas is going to finish debugging while I'm on the RISCV summit next week.
 2023-11-02 12:07:42 -05:00
Rose Thompson
7ba891f607 Progress. I think the remaining bugs are in the regression test's signature. 2023-11-01 17:51:48 -05:00
naichewa
9aa8a7af3e comments, more test cases 2023-11-01 01:26:34 -07:00
Rose Thompson
5660eff57d Working through issues with the psill logic. 2023-10-31 18:50:13 -05:00
Rose Thompson
4984b3935f Progress 2023-10-31 14:50:33 -05:00
Rose Thompson
5ca428d6a8 Fixed bugs in misaligned test. 2023-10-31 12:49:35 -05:00
Rose Thompson
c061440141 First stab at the misaligned test. 2023-10-31 12:30:10 -05:00
naichewa
7dd3f24d6c Merge branch 'main' into spi 2023-10-30 17:01:41 -07:00
naichewa
2330f4ee63 hardware interlock 2023-10-30 17:00:20 -07:00
Rose Thompson
2241976d29 Updated mmu to not generate trap on cacheable misaligned access when supported. 
Updated tests with David's help.
 2023-10-30 18:26:11 -05:00
David Harris
f6a7f707bd Fixed test cases for medeleg issue 444. Also added a COMPRESSED_SUPPORTED parameter true when C or Zca is supported, and use this to get compressed hardware such as the spill logic and the +2 adder. 2023-10-30 09:56:17 -07:00
Rose Thompson
0fd5b3b2ce Updated comments in the cboz tests. 2023-10-20 15:15:47 -05:00
Rose Thompson
5a4028064a Updated comments for the cbom tests. 2023-10-20 15:13:52 -05:00
naichewa
0ff9ce527d Merge branch 'main' into spi 2023-10-16 22:59:50 -07:00
David Harris
ac4216b43d Incorporated new AMO tests from riscv-arch-test 2023-10-16 10:25:45 -07:00
David Harris
6245748ed7 Added CSR permission tests for mconfigptr, menvcfg, mseccfg, etc. 2023-10-15 15:31:03 -07:00
David Harris
b4891d88db Added WALLY minfo test for rv32 2023-10-15 06:48:22 -07:00
David Harris
434d6b2c5c minfo test working again with mconfigptr for RV64 2023-10-15 06:41:52 -07:00
naichewa
aa5abfc8e8 always working after reg bit swizzle changes 2023-10-13 14:22:32 -07:00
naichewa
f231c3d3a3 correct delay0, fmt register test entries 2023-10-12 15:13:23 -07:00
naichewa
d5d4f9d044 transferred spi changes in ECA-authorized commit 2023-10-12 13:36:57 -07:00
David Harris
d526d28804 Added MENVCFG.HADE bit and updated SVADU to depend on this bit 2023-10-04 09:34:28 -07:00
Ross Thompson
9ff3642c6c Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-09-05 11:12:00 -05:00
David Harris
9747d122d2 tlbNAPOT hangs due to PBMT making instruction memory uncacheable, and spill logic not working there. Fixed TLBLRU to update recently used on TLBHit rather than CAMHit. Moved coverage exclusions to proper line in pmachecker 2023-09-02 12:56:36 -07:00
David Harris
e75ceb044f Improved tlb and controller coverage; fixed exclusions on broken lines 2023-08-31 00:27:47 -07:00
David Harris
1642ad2bad Improved NAPOT test coverage 2023-08-30 21:04:36 -07:00
Ross Thompson
12c3c98824 Extended the CBOM test to cover a 4 way set associative cache with 4KiB ways. 2023-08-30 11:29:44 -05:00
David Harris
91429f3f02 Initial TLB NAPOT tests 2023-08-29 12:39:24 -07:00
David Harris
8d3ff59673 Completed basic tests of svnapot and svpbmt 2023-08-28 06:57:35 -07:00
David Harris
0e16203cd8 Merge pull request #393 from ross144/main 
Implemented and tested CBOZ instruction
 2023-08-24 19:17:38 -07:00
David Harris
c45fbe1ffe Merge pull request #394 from harshinisrinath1001/main 
Improved testing of csri with priv.S!
 2023-08-24 19:16:50 -07:00
harshinisrinath
c9112ff18d Improved testing of csri with priv.S 2023-08-24 18:39:15 -07:00
Ross Thompson
cd3349bd26 Added rv32 cboz test. 2023-08-24 17:02:53 -05:00
Ross Thompson
914b6f9734 Now have CBOZ instructions working! 2023-08-24 16:47:35 -05:00
Ross Thompson
7d51690b7c Oups forgot to include the 32-bit cbom test in previous commit. 2023-08-24 09:04:41 -05:00
David Harris
d801916d97 Merge pull request #383 from ross144/main 
Adds Zicbom support for D-cache only.  I-cache not yet supported.  Tests 32 and 64 bit versions.  Please rebuild regressions wally32 and wally64.  To save rebuild time edit lines 11-12 of tests/riscof/Makefile
 2023-08-21 13:32:00 -07:00
David Harris
409abbf443 Merge pull request #381 from harshinisrinath1001/main 
Tried to improve coverage of CSRI with priv.S
 2023-08-21 13:28:39 -07:00
Ross Thompson
310b700550 Have a working 32 bit cbom test! 2023-08-21 13:46:09 -05:00
Ross Thompson
d4c6ba627d Working CBO tests for 64 bit! 2023-08-21 12:55:07 -05:00
Ross Thompson
5ed096e4bc Made a bunch of progress towards getting cbo instructions tested. 2023-08-21 11:46:21 -05:00
harshinisrinath
3d3d15077b cleared stimer interrupt 2023-08-20 15:42:27 -07:00
harshinisrinath
fdb7abec06 tried to improve testing of csri in privileged module 2023-08-20 15:40:02 -07:00
David Harris
2738423441 Improved CSRU coverage with priv.S 2023-08-20 12:49:31 -07:00
harshinisrinath
7494ce06eb wrote testcase to write into FSCR 2023-08-20 12:10:08 -07:00
Ross Thompson
05d590b0b9 Fixed issue when with flush miss. 2023-08-18 16:36:13 -05:00
Ross Thompson
fc3fccafe9 Now we have invalidate, clean, and flush working. 2023-08-18 16:32:22 -05:00
Ross Thompson
4eeba9bed9 Added cbom test to custom. Needs to be moved to wally-riscv-arch-tests. 2023-08-18 15:59:39 -05:00
harshinisrinath
b4cfdf3393 Fixed bug and tried to reset menvcfg to improve testing of csri in priv. 2023-07-30 16:40:06 -07:00
harshinisrinath
413a104b6c Merge branch 'main' of https://github.com/openhwgroup/cvw into main 2023-07-23 11:59:43 -07:00
Ross Thompson
a89a1e675c Merge branch 'boot' into mergeBoot 
Merges Jacob's new sdc controller into wally.
 2023-07-21 17:43:45 -05:00
Jacob Pease
380d96b359 Working new boot process. Buildroot package for sdc. 2023-07-20 14:15:59 -05:00
Jacob Pease
b3aaa87cba Modified bootloader to access GUID partitions. SDC interrupt to PLIC. 
Since writing an SD card image generation script, the bootloader
needed to be altered to access individual binaries from specific
partitions. A new file, gpt.c with it's header gpt.h, have been added
to the bootloader to facilitate this.

The SDC has been added to the device tree for the VCU108
board. Additionally the SDC interrupt signal was added to the PLIC
node in the device tree. The PLIC itself  was modified to accept the
SDC interrupt signal.
 2023-07-14 13:36:44 -05:00
harshinisrinath
8adfcebb4f Merge branch 'main' of https://github.com/openhwgroup/cvw into main 2023-07-13 13:00:58 -07:00
Kevin Kim
f6a3474550 fixed bug in testvector extract script 
-old script skips first 2 lines in rv32m case, new script only skips first line
- prior code skipped every other line in the reference file, so it only generated half the test vectors, with half of them having the wrong answer
- prior code also opened test vector file to be written to in "append" mode, and I changed to write mode (so that the script overwrites instead of adding to an existing file)
 2023-06-22 09:13:22 -07:00
harshinisrinath
f9d3944cc5 Improved testing of pmd in priv. 2023-06-16 17:13:54 -07:00
harshinisrinath
d018357914 Improve test coverage on ieu fw. 2023-06-16 16:09:48 -07:00
David Harris
c137a1c8cf Fixed timer interrupt testing 2023-06-09 17:20:41 -07:00
David Harris
f68b9c224a Fixed WALLY-trap test case to use menvcfg 2023-06-09 15:24:26 -07:00
David Harris
b70b0c7c5e Added support for menvcfg and senvcfg, including menvcfg.STCE for supervisor timer compare 2023-06-09 14:40:01 -07:00
Ross Thompson
4ddbbd6948 Merge pull request #314 from davidharrishmc/dev 
Make and FP script improvements
 2023-06-06 12:38:26 -04:00
James Stine
ac3253203d Update fcvt tests for l.s/lu.s and s.l/s.lu that were missing 2023-06-05 11:03:59 -05:00
David Harris
1831dfccc2 Fixed paths in creating division test vectors 2023-05-31 06:30:41 -07:00
David Harris
b5f70013b1 Clean up combined int/fp vector creation 2023-05-30 14:01:12 -07:00
Jacob Pease
40f81d5da6 The Vivado-RISC-V SDC works. Wally is now booting through it. 2023-05-26 15:42:33 -05:00
David Harris
b4c9998b26 Increased timeout for riscof because it is so slow 2023-05-23 15:37:09 -07:00
David Harris
19096a812a Added Zifencei ISA to tests where necessary to support new compiler 2023-05-16 11:18:27 -07:00
David Harris
0a7a159d69 Added Zicsr and zifencei to RVTEST_ISA in custom tests where necessary to make them compile 2023-05-14 06:58:29 -07:00
David Harris
0cc8f9fd15 Fixed riscof scripts that were removing zicsr from compiler misa 2023-05-14 04:19:08 -07:00
David Harris
67a089104c Defined empty RVMODEL interrupt macros to make riscof warnings go away 2023-05-14 03:36:28 -07:00
Kevin Thomas
0c9b7dcce7 Comment tlbGBL more discriptively 
Reduce redundant instructions
 2023-05-04 19:13:47 -05:00
David Harris
ec3518673e Merge branch 'main' into main 2023-04-28 07:51:32 -07:00
Liam Chalk
028d19bbfa Merge branch 'main' into main 2023-04-27 21:49:01 -07:00
Kevin Wan
39c9cd5ee9 added tests for pmppriority module 2023-04-27 16:12:43 -07:00
David Harris
15fb5fa2ac Update tlbASID.S 
fixed comment about restoring ASID to 0
 2023-04-27 14:32:57 -07:00
Noah Limpert
4ec31de316 complete camline coverage on IFU and LSU 2023-04-27 14:26:10 -07:00
Liam
4d8eafd27d Pmpadrdecs test cases changing AdrMode to 2 or 3 
Setting AdrMode to 2 or 3 for pmpadrdecs[0-4] writing values to pmpcfg0 to change AdrMode to 2 or 3
Also exclusion for pmpadrdecs[0] coverage case for PAgePMPAdrIn being hardwired to 1 in pmpadrdec.sv
 2023-04-27 12:23:35 -07:00
Alexa Wright
09095422d0 Merge branch 'openhwgroup:main' into main 2023-04-26 16:26:30 -07:00
Alexa Wright
59d913949f Excluded and added coverage for WFI test case. 2023-04-25 17:06:57 -07:00
Liam
7bf2ee5418 pmpaddr0 and pmpaddr2 test cases 
Writing 0x00170000 and 0x17000000 to pmpaddr0 and pmpaddr2.
Increased IFU coverage from 83.53% to 83.68% and LSU coverage from 93.29% to 93.45%.
 2023-04-25 15:37:04 -07:00
David Harris
086556310c Attempted to cause interrupt during fdivsqrt. Fixed enabling fpu in fpu.S. Fdivsqrt exclusions for coverage. 2023-04-22 12:22:45 -07:00
Liam
c2f441724b pmpcfg test cases 
Increased IFU coverage from 83.37% to 83.53% and LSU coverage from 93.14% to 93.28%.
 2023-04-21 20:43:37 -07:00
Noah Limpert
a0e71c26cb Add in a test that makes match 3 = 0 for all tlb lines 2023-04-20 14:50:06 -07:00
Noah Limpert
7ca44de126 Commiting changes to add coverage to ASID, Global, Megapage size checks. 2023-04-20 14:38:13 -07:00
Liam
4f57dca0dc Add pmpcfg test cases increasing IFU coverage 2023-04-19 11:58:22 -07:00
David Harris
4cbffd7972 Merge branch 'main' into coverage4 2023-04-19 06:16:07 -07:00
David Harris
b63dff098a Merge branch 'main' into main 2023-04-19 04:50:12 -07:00
Alec Vercruysse
b3a3af8ed3 add D$ test case to trigger a FlushStage while SetDirtyWay=1 
This hits some conditional coverage in each cacheway.
A cache store hit happens at the same time as a StoreAmoMisalignedFault.
 2023-04-19 01:34:01 -07:00
Alec Vercruysse
cd803bfa44 Cover CacheWay edge case: CacheDataMem we=1 while ce=0. 
This test basically triggers an i$ miss during a d$ (hit) store
operation. It requires some tricky timing (e.g. a flushD right
before the relevant store). I use a script to generate the test.
 2023-04-19 01:34:01 -07:00
Liam
d74768ce04 Add test cases for pmpcfg.S 2023-04-18 23:06:52 -07:00
Kevin Wan
b5a3ff2d2d a 2023-04-18 22:09:50 -07:00
Kevin Wan
c91784bd5a Merge branch 'main' of https://github.com/koooo142857/cvw into main 2023-04-18 21:55:06 -07:00
koooo142857
c9018b8204 Merge branch 'openhwgroup:main' into main 2023-04-18 21:53:46 -07:00
Kevin Wan
771124e265 Completely covers all PMPCFG_ARRAY_REGW cases 2023-04-18 21:50:48 -07:00
Kevin Wan
1bdae2285d PMPCFG_ARRAY_REGW cases 2023-04-18 18:43:50 -07:00
Miles Cook
5e45fef838 Increase of TLB coverage in IFU 2023-04-17 18:35:03 -07:00
Diego Herrera Vicioso
16fd17be39 Added test coverage for reads to HPM counters and added exclusions for impossible cases in rv64gc 2023-04-15 23:13:39 -07:00
Dygore
cac9c2dc37 Added multiple tests to increase FPU coverage 2023-04-14 14:41:05 -05:00
Dylan
d7936a9214 Merge branch 'openhwgroup:main' into main 2023-04-14 00:36:57 -05:00
Dygore
69b4751162 Added tests for full coverage of the FPU result sign module 2023-04-14 00:36:12 -05:00
Noah Limpert
6a23bbea9d add back K. Box and M. Cook Lsu test 2023-04-13 17:50:18 -07:00
Noah Limpert
3683139637 make pull request more clean 2023-04-13 17:44:09 -07:00
Noah Limpert
b35d5bdbdb Revert "instantiate 5 4KiB arrays, aim to thrash all 4 ways" 
This reverts commit 6acf1dadda.
 2023-04-13 17:40:39 -07:00
Noah Limpert
d012715a60 Revert "Test File for Pull Request, Attempt to fill all four ways" 
This reverts commit e887341c80.
 2023-04-13 17:28:37 -07:00
Noah Limpert
034dabee54 Merge branch 'main' of https://github.com/openhwgroup/cvw into main 2023-04-13 17:00:48 -07:00
Noah Limpert
a0a9d35d19 update tests.vh, add tlbKP to load all lines of tlb 2023-04-13 15:13:55 -07:00
Dygore
4854e09124 Added a test for denormalized FP numbers 2023-04-13 16:39:27 -05:00
Noah Limpert
276ce87582 Merge branch 'main' of https://github.com/openhwgroup/cvw into main 
pull in changes to trap handler so that permissions should change correctly
 2023-04-13 12:34:27 -07:00
Alexa Wright
23d0d45bf6 Fixed exception handling to handle ecalls properly 2023-04-13 09:23:32 -07:00
Kip Macsai-Goren
34200e8c76 restored original virt mem tests when svadu is not supported 2023-04-11 18:47:08 -07:00
Kip Macsai-Goren
c4766c8a02 renamed virt mem tests to include svadu 2023-04-11 18:46:37 -07:00
Kip Macsai-Goren
b2d6084eea removed unnecessary 'deadbeef's at the end of reference outputs 2023-04-11 18:32:04 -07:00
Kip Macsai-Goren
a82c0a7780 Modified virt mem tests to do correct r/w when svadu is enabled 2023-04-11 18:08:30 -07:00