Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-01-27 15:04:36 +00:00
Code Issues Packages Projects Releases Wiki Activity
1,239 Commits 5 Branches 2 Tags 52 MiB
ef2bcf6ea7
Commit Graph

288 Commits

Author SHA1 Message Date
Jarred Allen
507d8ed120 Merge branch 'main' into cache 2021-03-22 14:50:22 -04:00
Noah Boorstin
c4fb51fad1 regression: expect 200k instead of 100k busybear instrs 
and a minor busybear bugfix
 2021-03-22 14:47:52 -04:00
Jarred Allen
bab0e3b90f Change busybear testbench to reflect new location of InstrF 2021-03-20 18:20:27 -04:00
Jarred Allen
639a718312 Fix conflicts in ahb-waves that snuck through manual merging 2021-03-20 17:16:50 -04:00
Jarred Allen
50c961bbe4 Merge changes from main 2021-03-18 18:58:10 -04:00
Jarred Allen
bf2fbf49ee Add icache's read request to ahb wavs 2021-03-18 18:52:03 -04:00
bbracker
df51d9908d AHB bugfixes and sim waveview refactoring 2021-03-18 18:25:12 -04:00
bbracker
11ba96f2e3 maybe AHB works now 2021-03-18 17:47:00 -04:00
Shreya Sanghai
dfc86539cc Merge branch 'gshare' into main 
Conflicts:
	wally-pipelined/regression/wave.do
 2021-03-18 17:25:48 -04:00
Ross Thompson
181a28e875 Fixed minor bug with the size of gshare. 2021-03-18 16:00:09 -05:00
Teo Ene
0ff785549e Switched coremark to RV64IM 2021-03-17 22:39:56 -05:00
Jarred Allen
e39ead0460 Merge branch 'main' into cache 
Conflicts:
	wally-pipelined/testbench/testbench-imperas.sv
 2021-03-17 16:40:52 -04:00
Teo Ene
29634f1475 Temporarily reverted my last few commits 2021-03-17 15:16:01 -05:00
Teo Ene
e6661ea26a fix to last commit 2021-03-17 15:07:02 -05:00
Teo Ene
083a24c06b addition to last commit 2021-03-17 14:52:31 -05:00
Elizabeth Hedenberg
bccd37d778 fixing coremark branch prediction 2021-03-17 15:15:55 -04:00
Elizabeth Hedenberg
a3b2ffb2c9 Merge branch '3_3_2021' into main 
Making sure coremark works with spring break changes
 2021-03-17 14:11:37 -04:00
Ross Thompson
7bc95ba073 Fixed issue with sim-wally-batch. Are people still using this script? 2021-03-17 11:17:52 -05:00
Ross Thompson
0e2352a6de Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-17 11:07:57 -05:00
Ross Thompson
31ad619a21 Added possibly working OSU test bench as a precursor to running a bp benchmark. 
Fixed a few bugs with the function radix.
 2021-03-17 11:06:32 -05:00
Jarred Allen
ed68d8240b Undo accidental change 2021-03-16 18:16:00 -04:00
Jarred Allen
ba7bfa9056 Condense the parallel and non-parallel wally-pipelined-batch.do files into one 2021-03-16 18:15:13 -04:00
Jarred Allen
6e7fc07fcf Change busybear to only check that first 100k instructions load 2021-03-16 17:43:39 -04:00
Jarred Allen
662ab53746 Merge remote-tracking branch 'origin/main' into cache 2021-03-15 19:08:25 -04:00
Noah Boorstin
cd58f8a12d remove regression-wally.sh 2021-03-15 19:03:57 -04:00
Ross Thompson
8e51935082 Converted branch predictor preloads to use system verilog rather than modelsim's load command. 2021-03-15 12:39:44 -05:00
Ross Thompson
d341e2d5cb Fixed the parallel script so the rv64ic passes. 
rv32ic and busybear still have issues.
 2021-03-15 12:04:59 -05:00
Jarred Allen
003242ae8a Merge upstream changes 2021-03-14 14:57:53 -04:00
Jarred Allen
c2f2caa3f6 Get non-jump case working 2021-03-14 14:46:21 -04:00
Ross Thompson
0edaa625e3 Fixed the issue with the batch mode not working after adding the function radix. 2021-03-12 20:16:03 -06:00
Ross Thompson
ccaaa829ce Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-12 14:58:04 -06:00
Ross Thompson
0637874cac Cleanup of the branch predictor flush and stall controls. 2021-03-12 14:57:53 -06:00
Ross Thompson
b1d1f3995c Improve version of the function radix which does not cause the wave file rendering to slow down. 2021-03-11 17:12:21 -06:00
Noah Boorstin
be0bd317e9 test regression script: add commented out rv32ic tests 2021-03-11 12:57:54 -05:00
Noah Boorstin
641a320894 add rv32ic regression test 2021-03-11 12:40:29 -05:00
Noah Boorstin
2dfb944d15 test regression script: parallalize better 2021-03-11 12:25:20 -05:00
Noah Boorstin
b13365365b test regression script: try adding verilator checking also 2021-03-11 07:32:31 +00:00
Noah Boorstin
8717f3604b try adding delays to test regression script 2021-03-11 06:59:50 +00:00
Noah Boorstin
c5b6ca4cc6 this is just a test for now, try to reimplement regression-wally in bash 2021-03-11 06:45:45 +00:00
Ross Thompson
f1f7884e10 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-10 15:37:02 -06:00
Ross Thompson
149c9aa0f2 Added debug option to disable the function radix if not needed. 
Function radix slows the simulation by 70 to 76 s (8.5%) for the rv64i tests.
 2021-03-10 15:17:02 -06:00
Ross Thompson
4d7e926dbb I finally think I got the function radix debugger working across both 32 and 64 bit applications. 2021-03-10 14:43:44 -06:00
Ross Thompson
7b7cacbaf0 Finally I think I have the function radix mapping across all applications correctly. I still need to clean up the code a bit so it is easier to understand. 2021-03-10 11:00:51 -06:00
Jarred Allen
c0ee17b6ac Merge upstream changes 2021-03-09 21:20:34 -05:00
David Harris
0baa004bb4 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-09 09:28:32 -05:00
David Harris
bea8ac6d59 WALLY-LRSC atomic test passing 2021-03-09 09:28:25 -05:00
Noah Boorstin
9274d09ae2 busybear: better instrF checking 
So this now checks instrF only when StallD is low. @kaveh I'd love your
opinion on this. I don't know if this is a good idea or not. Ideally we
should probably be checking InstrRawD instead, but I kind of want to stay
checking the instr in the F stage instead of D for now. Idk if this is worth
staying in F, I can't really see any big downsides to checking the instruction in
D except that PCD isn't an external signal, but neither is StallD, so.....
Anyway I'd love others' thoughts on this
 2021-03-08 19:48:12 +00:00
Noah Boorstin
08e3691e59 busybear: make a second .do file with better optimization for command line mode 2021-03-08 19:35:00 +00:00
Noah Boorstin
1fc00d41c2 busybear: load mem files from verilog instead of .do 2021-03-08 19:26:26 +00:00
Ross Thompson
a3759f585d Updated the paths to the branch predictor memory preloads for busy bear. 2021-03-05 15:36:00 -06:00
Ross Thompson
d6bc34121f Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-05 15:27:22 -06:00
Ross Thompson
9a93193d6a Oups. I forgot to update other do files with the commands to preload the branch predictor memories. 2021-03-05 15:23:53 -06:00
Noah Boorstin
d3bf36b15f busybear: add branch preditor loading to do file 
(sorry to add more loading to the do instead of less)
 2021-03-05 21:01:41 +00:00
Noah Boorstin
f0a103687e Merge branch 'main' into busybear 2021-03-05 20:27:19 +00:00
Noah Boorstin
6981907521 fix wally-pipelined-batch.do to match wally-pipelined.do 2021-03-05 20:27:01 +00:00
bbracker
420c9a11c2 refactored sim file 2021-03-05 14:25:16 -05:00
bbracker
62dd9e3075 first merge of ahb fix 2021-03-05 14:24:22 -05:00
Noah Boorstin
7208b9bcf2 busybear: better implenetation of sim-busybear-batch 2021-03-05 00:39:03 +00:00
Noah Boorstin
cfcd7d1518 busybear: make imperas tests work again 2021-03-04 22:44:49 +00:00
Jarred Allen
b0f4d8e8d4 Remove rd2, working for non-compressed 2021-03-04 16:46:43 -05:00
Noah Boorstin
fde94f9057 Merge branch 'main' into busybear 
Conflicts:
	wally-pipelined/src/uncore/imem.sv
 2021-03-04 20:16:03 +00:00
Ross Thompson
619bbd9d83 Merge branch 'bp' into main 
Concerns:
1. I don't think the correct data buses are going to the multiplier.
2. I'm not sure the FlushF signal is correct.
 2021-03-04 13:35:46 -06:00
Teo Ene
95ce4b7daa Edited assemby of bare-metal coremark to make it run 2021-03-04 07:45:40 -06:00
Teo Ene
2723b21988 Linux CoreMark and baremetal CoreMark split into two separate tests/configs 2021-03-04 07:44:33 -06:00
Teo Ene
80f6d6c944 Linux CoreMark is operational 2021-03-04 05:58:18 -06:00
Teo Ene
0c009fb1e6 In the process of updating coremark.RV64I program to work with Dr. Harris's perl script. Commiting to make it easier to switch branches 2021-03-04 01:27:05 -06:00
Teo Ene
a82a123069 Implemented fix disucssed with Elizabeth 2021-03-03 18:17:53 -06:00
Teo Ene
b50faef94d Updated coremark .do file for easier debugging 2021-03-03 15:10:39 -06:00
Teo Ene
d02e22feac Updated coremark .do file for easier debugging 2021-03-02 17:23:39 -06:00
Noah Boorstin
beb2beabfd busybear: add sim-busybear and sim-busybear-batch based on sim-wally 2021-03-01 21:01:15 +00:00
Noah Boorstin
923489fe16 busybear: probably discovered bug in ahb code 2021-03-01 20:56:04 +00:00
Noah Boorstin
b3247eadd2 busybear: more adapting to new memory system 2021-03-01 18:50:42 +00:00
Noah Boorstin
f11b3108d8 busybear: fix bootram range 2021-03-01 17:45:21 +00:00
Noah Boorstin
a267115635 Merge branch 'main' into busybear 2021-02-28 20:45:08 +00:00
Noah Boorstin
17715085ba busybear: start preloading bootmem 2021-02-28 20:43:57 +00:00
Noah Boorstin
932bc0ef85 busybear: check instead of providing InstrF 2021-02-28 16:46:53 +00:00
Ross Thompson
6191fcb1af Shreya and I found a bug with the exeuction of JAL and JALR instructions. The link was only set in the writeback stage. Once the branch predictor started correctly predicting JAL(R)s the ALU and forwarding logic need to have the PCLinkE at the execution stage in case an instruction in the next two clocks need the data. 2021-02-26 20:12:27 -06:00
Ross Thompson
c2cf3f9fb6 Updating the test bench to include a function radix. Not done. 2021-02-26 19:43:40 -06:00
David Harris
73920282af Eliminated flushing pipeline on CSR reads 2021-02-26 17:00:07 -05:00
kaveh pezeshki
e8b306bcba merged with main to integrate with AHB 2021-02-26 05:37:10 -08:00
Noah Boorstin
4c7b185d90 busybear: add main ram loading, better instr checking also 2021-02-26 20:26:54 +00:00
Teo Ene
8491deb1a9 Changed .do file back to run all 2021-02-25 09:58:54 -06:00
David Harris
cd4ba8831c Merged bus into main 2021-02-25 00:28:41 -05:00
Teo Ene
cfd45a46c3 Added provisional coremark files from work with Elizabeth 2021-02-24 20:07:07 -06:00
Noah Boorstin
ddaf67c043 busybear: preload bootram 
thanks to Prof Stine for the .do file commands

@kaveh can you check line 201? it does nothing, but things break when
I remove that line
 2021-02-24 18:46:09 +00:00
Noah Boorstin
7b7e87bd0b busybear: start adding ram 2021-02-23 22:01:23 +00:00
Noah Boorstin
c42c485377 busybear: instantiate soc instead of hart 2021-02-23 18:59:06 +00:00
kaveh pezeshki
e146946e58 Merge remote-tracking branch 'origin/tlb_toy' into busybear 2021-02-22 02:23:01 -08:00
Ross Thompson
c856003f73 RAS needs to be reset or preloaded. For now I just reset it. 
Fixed bug with the instruction class.
Most tests now pass.  Only Wally-JAL and the compressed instruction tests fail.  Currently the bpred does not support compressed.  This will be in the next version.
 2021-02-19 20:09:07 -06:00
Ross Thompson
597dd1e7e6 Added FlushF to hazard unit. 
Fixed some typos with the names of signals in the branch predictor.  They were causing signals to be not set.  Note there is a modelsim flag which prevents it from compiling if a logic is undefined.
I will look this up and add it to the compiler.
 2021-02-19 16:36:51 -06:00
Ross Thompson
06e975ac2f minor change to wave file. 2021-02-19 09:08:13 -06:00
Ross Thompson
7d6093b302 Hacked the sram memory models to reset their internal registers. This allows the simulation to run but is only temporary. 
About 149307ns of simulation run.
 2021-02-18 21:32:15 -06:00
Ross Thompson
8cbc9f7e51 Wrote a bash script to generate custom modelsim radix which maps instruction addresses into human readable lables. 
Once combined with some simulation verilog this will display the current function in modelsim.
 2021-02-17 22:20:28 -06:00
Ross Thompson
bbe0db3ebe Integrated the branch predictor into the hardward. Not yet working. 2021-02-17 22:19:17 -06:00
Noah Boorstin
84d856d1e5 busybear: allow testbench to ignore lack of MMU for now 
I'd really like to go over this with someone else, not sure if this is
a good thing to be doing

If it is, we're at 1M instructions!
 2021-02-12 20:08:56 +00:00
bbracker
deb7780897 bus rw bugfix and peripherals testing 2021-02-12 00:02:45 -05:00
Teo Ene
5f84ed407c Adding coremark testbench and do files that Elizabeth has written thus far, on this account, in order to avoid merge conflicts 2021-02-10 20:48:39 -06:00
David Harris
842c374de9 Debugging instruction fetch 2021-02-09 11:02:17 -05:00
David Harris
33110ed636 Data memory bus integration 2021-02-07 23:21:55 -05:00
Noah Boorstin
01b1b1705d Busybear: next week of updates 
- move parsed instructions out of git, to /courses/e190ax/busybear_boot
 - parsed first 1M instructions, and now parse from split GDB runs
 - now at about 230k instructions, can't progress further for now since atomic instructions
   aren't implemented yet
 2021-02-07 03:14:48 +00:00
Noah Boorstin
c03f69fb80 Change CSR reset and available bits to conform to OVPsim 
Now actually keeping perfectly in line with OVP for the first 100k instrs. Yay.
 2021-02-04 22:03:45 +00:00
Jarred Allen
088fbbcbf0 Change busybear test to use work-busybear library 2021-02-03 11:12:47 -05:00
Jarred Allen
e5bd749e2a Refactor regression test 2021-02-02 17:22:29 -05:00
Noah Boorstin
d2064987e9 Add busybear testbench to nightly regression checking 
If you don't like how I did this please feel free to undo it
 2021-02-02 22:05:35 +00:00
Jarred Allen
da43b2be53 Fix intermittent errors caused by weird library stuff 2021-02-02 11:20:09 -05:00
Jarred Allen
f143518b23 Fix issues in parallel regression testing 2021-02-01 23:29:03 -05:00
Noah Boorstin
d592db79c9 busybear: change register file checking to only store register changed 
this should make parsedRegs.txt much smaller
 2021-02-02 01:27:43 +00:00
Jarred Allen
5cf3d188c6 Parallelize regression-wally.p 2021-02-01 15:40:27 -05:00
Noah Boorstin
a82f8977c6 busybear: NOP out floating point instructions for now 
Why does linux even try to do float stuff doing booting??
also, now runs the first 100k instructions!
 2021-01-30 19:52:47 +00:00
Noah Boorstin
cca60ed06d update busybear testbench to conform to new structure 
aaaaaaaaaaaaaaaaaahhhh so many changes

also the testbench now uses another internal signal,
which I don't like, but I can't think of a better option rn
 2021-01-30 19:19:00 +00:00
David Harris
07af481b67 Reorganized src hierarchically 2021-01-30 11:50:37 -05:00
David Harris
9511dcac84 Connected AHB bus to Uncore 2021-01-29 23:43:48 -05:00
David Harris
6d5b01357d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-01-29 15:38:01 -05:00
David Harris
d104e5a4be Moving data memory to uncore 2021-01-29 15:37:51 -05:00
Noah Boorstin
7183910c84 update busybear testbench to conform to new structure 2021-01-29 17:46:50 +00:00
Noah Boorstin
84e4193db6 busybear testbench: test on first 100k instrs 
currently gets about 47k instrs correctly
also fix gdb parsing to avoid accidently matching on function names
 2021-01-29 00:14:23 -05:00
Noah Boorstin
c4964352f0 busybear: simulate first 10k instructions 
I know we need to add CSR checking sometime soon
Also I'm a bit sketpical this is all working properly, and that no new bugs
were uncovered from 1k instrs to 10k instrs
 2021-01-28 19:44:58 -05:00
Noah Boorstin
96ceac0e80 busybear: fix misaligned writing checking 2021-01-28 19:35:09 -05:00
Noah Boorstin
df1d174aea busybear: add more test instructions 
currently testing first 1k instrs
 2021-01-28 16:41:37 -05:00
Noah Boorstin
cbab07967a more of the same fixes 2021-01-28 16:26:15 -05:00
Noah Boorstin
03cea6e29b more misaligned read fixing 
I'm getting fairly concerned about this, I feel like
this should only work if the memory ignores the lower 3 or 4 bits of the adr
 2021-01-28 16:14:35 -05:00
Noah Boorstin
e65166bec5 busybear testbench: understand bytemask for writes 2021-01-28 15:42:47 -05:00
Noah Boorstin
9a45b49536 busybear: ret is only 1 word 2021-01-28 14:47:40 -05:00
Noah Boorstin
5a5237b908 add speculative exception for compressed instructions 2021-01-28 14:40:35 -05:00
Noah Boorstin
632fecf43a testbench now understands lw not aligned to 8 bytes 
also busybear now has first 500 instead of 100 instrs
and prints current instrs less
 2021-01-28 13:33:22 -05:00
Noah Boorstin
be3d024527 Busybear test now processes first 100 instrs correctly! 
- changed test parser to recognize lw in addition to lw

also, added temporary questa files (wlft*) to .gitignore
 2021-01-28 01:19:27 -05:00
Noah Boorstin
ed85fda42a fix memory write address decoding for busybear tests 2021-01-28 01:19:26 -05:00
Noah Boorstin
840528a05f update busybear testbench to conform to new structure 2021-01-27 23:42:19 -05:00
David Harris
9d821aab0f Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-01-27 22:49:55 -05:00
David Harris
37a58cea17 Repartitioned with Instruction Fetch Unit, Integer Execution Unit 2021-01-27 22:49:47 -05:00
Noah Boorstin
74e57a8472 update busybear testbench to conform to new structure 2021-01-27 12:54:09 -05:00
David Harris
092edf953e Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-01-27 06:40:39 -05:00
David Harris
4318629b32 Repartitioned datapath and controller into ieu 2021-01-27 06:40:26 -05:00
Noah Boorstin
91564c7ab1 show instruction assembly in waveform 2021-01-26 12:34:12 -05:00
Noah Boorstin
91dcffa26f Update busybear tests to conform to new directory structure 2021-01-25 20:37:18 -05:00
Noah Boorstin
09c92a6b5d Fixed mem write checking 
now passes around 50 instructions!
 2021-01-25 20:07:08 -05:00
Noah Boorstin
05d4f2d33d fix speculation ignoring for PC fetching 2021-01-25 20:07:06 -05:00
David Harris
bf07ec92b5 Added test configurations 2021-01-25 11:28:43 -05:00