Ross Thompson a3759f585d Updated the paths to the branch predictor memory preloads for busy bear.		2021-03-05 15:36:00 -06:00
..
regression-wally.py	Oups. I forgot to update other do files with the commands to preload the branch predictor memories.	2021-03-05 15:23:53 -06:00
sim-busybear	busybear: add sim-busybear and sim-busybear-batch based on sim-wally	2021-03-01 21:01:15 +00:00
sim-busybear-batch	busybear: better implenetation of sim-busybear-batch	2021-03-05 00:39:03 +00:00
sim-wally	Added test configurations	2021-01-25 11:28:43 -05:00
sim-wally-batch	Added test configurations	2021-01-25 11:28:43 -05:00
twoBitPredictor.txt	Wrote a bash script to generate custom modelsim radix which maps instruction addresses into human readable lables.	2021-02-17 22:20:28 -06:00
wally-busybear.do	Updated the paths to the branch predictor memory preloads for busy bear.	2021-03-05 15:36:00 -06:00
wally-coremark.do	Oups. I forgot to update other do files with the commands to preload the branch predictor memories.	2021-03-05 15:23:53 -06:00
wally-peripherals-signals.do	refactored sim file	2021-03-05 14:25:16 -05:00
wally-peripherals.do	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-03-05 15:27:22 -06:00
wally-pipelined-batch-parallel.do	Oups. I forgot to update other do files with the commands to preload the branch predictor memories.	2021-03-05 15:23:53 -06:00
wally-pipelined-batch.do	Updated the paths to the branch predictor memory preloads for busy bear.	2021-03-05 15:36:00 -06:00
wally-pipelined-ross.do	Oups. I forgot to update other do files with the commands to preload the branch predictor memories.	2021-03-05 15:23:53 -06:00
wally-pipelined.do	Oups. I forgot to update other do files with the commands to preload the branch predictor memories.	2021-03-05 15:23:53 -06:00
wave-all.do	Added FlushF to hazard unit.	2021-02-19 16:36:51 -06:00
wave.do	Shreya and I found a bug with the exeuction of JAL and JALR instructions. The link was only set in the writeback stage. Once the branch predictor started correctly predicting JAL(R)s the ALU and forwarding logic need to have the PCLinkE at the execution stage in case an instruction in the next two clocks need the data.	2021-02-26 20:12:27 -06:00