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1956 Commits

Author SHA1 Message Date
David Harris
4f7d9eee95 XMerge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-12-21 20:39:38 -08:00
Ross Thompson
b3ff4fe02e CacheEn enables reading or writing the cache memory arrays. This is only disabled if we have a stall while in the ready state and we don't have a cache miss. This is a cache hit, but we are stalled. 2022-12-21 22:13:05 -06:00
cturek
c405dcf0cb worked out some bugs with int div cycles 2022-12-22 02:22:01 +00:00
cturek
e441f90b32 Renamed signals to E and M stages, forwarded preprocessed n to fsm 2022-12-22 00:43:27 +00:00
Ross Thompson
d1aa5ba890 Updated cache fsm names to match book. 2022-12-21 16:49:53 -06:00
Ross Thompson
de161c675c Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2022-12-21 16:13:09 -06:00
Ross Thompson
0cb2cf9a5b Changed GatedStallF to GatedStallD. 2022-12-21 16:12:55 -06:00
David Harris
16c8655161 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-12-21 14:12:25 -08:00
David Harris
a5dc09c97f Added assertion about atomics needing caches 2022-12-21 13:57:28 -08:00
cturek
2c58fd42db Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-12-21 20:41:38 +00:00
David Harris
3562542728 comment cleanup 2022-12-21 12:39:09 -08:00
David Harris
ca949f2110 Only delegated bits of SIP are readable 2022-12-21 12:32:49 -08:00
cturek
14d9118802 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-12-21 19:35:57 +00:00
cturek
6761101645 fixed normshift calculations 2022-12-21 19:35:47 +00:00
David Harris
998f446e3c git push 
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
 2022-12-21 11:31:27 -08:00
David Harris
820e1ab510 Removed unused FPU signals 2022-12-21 11:31:22 -08:00
Ross Thompson
f6393d1288 Waiting on fix for wally64periph uart test. 
would like to remove vectored interrupt adder.
 2022-12-21 13:16:09 -06:00
Ross Thompson
c41d58bd29 Vectored interrupts now require 64 byte alignment. 
Eliminates adder.
 2022-12-21 12:05:49 -06:00
Ross Thompson
2b1e9f8bed The optimzied PC+2/4 logic still hanges on wally32priv. 2022-12-21 09:19:34 -06:00
Ross Thompson
a2329c8e9d Renamed PCPlusUpperF to PCPlus4F. 2022-12-21 09:18:30 -06:00
Ross Thompson
a6ffb4cef3 Added timeout check to testbench. 
A watchdog checks the value of PCW.  If it does not change within 1M cycles immediately stop simulation and report an error.
 2022-12-21 09:18:00 -06:00
Ross Thompson
3fc121ef70 Fixed minor bug in PLIC. reading interrupt source 0 should not return x. it should provide produce 0. 
Switched to even simplier PC+2/4 logic.
 2022-12-21 09:00:09 -06:00
Ross Thompson
968e174d68 Changes to wave file. 2022-12-21 08:41:47 -06:00
Ross Thompson
bc5d5e902a Comments about PC+2/4. 2022-12-21 08:35:43 -06:00
David Harris
28085ce8eb Clean up vecgtored interrupts 2022-12-20 16:53:09 -08:00
David Harris
88ee834c97 Converted tvecmux to structural 2022-12-20 16:24:04 -08:00
Ross Thompson
6152c028db Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2022-12-20 18:09:37 -06:00
Ross Thompson
2f0d20b8b0 privileged pc mux cleanup. 2022-12-20 18:05:44 -06:00
Ross Thompson
cba2ed64e5 Moved privileged pc logic into privileged unit. 2022-12-20 17:55:45 -06:00
David Harris
07dc11a508 IFU mux for CSRWriteFenceM conditional on ZICSR/ZIFENCEI 2022-12-20 15:38:30 -08:00
Ross Thompson
b4bdf446cc Implement FENCE.I as NOP when ZIFENCEI is not supported. 2022-12-20 17:34:11 -06:00
Ross Thompson
d9a1870a31 Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2022-12-20 17:11:35 -06:00
Ross Thompson
ef4ecbe62b Changed long names of vectored pcm signals. 2022-12-20 17:01:20 -06:00
David Harris
f03d4e6b5a Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-12-20 14:43:33 -08:00
David Harris
9133b3a7a4 FPU remove unused signals 2022-12-20 14:43:30 -08:00
Ross Thompson
be1bbf486e Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2022-12-20 16:36:44 -06:00
Ross Thompson
637df763ca Renumbered bits for PCPlusUpper. 2022-12-20 16:33:49 -06:00
David Harris
4c4b8db498 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-12-20 11:23:53 -08:00
David Harris
8f0ef29349 Memory cleanup 2022-12-20 11:22:26 -08:00
Ross Thompson
ca6076445b Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2022-12-20 12:58:59 -06:00
Ross Thompson
d35fc5e2a6 Reorganized IFU PCNextF logic. 2022-12-20 12:58:54 -06:00
David Harris
c26c3b76ea Renamed renamed sram to ram 2022-12-20 08:36:45 -08:00
David Harris
1ec62606f9 sram1p1rw cleanup 2022-12-20 02:57:51 -08:00
David Harris
0883736c88 Remoed unused bram modules 2022-12-20 02:40:45 -08:00
David Harris
9ad5552e89 Renamed SRAM2P1R1W to lower case 2022-12-20 02:09:55 -08:00
David Harris
b575f6242e Renamed SRAM2P1R1W to lower case 2022-12-20 02:09:36 -08:00
David Harris
0c10ec942a Replaced || and && with single ops 2022-12-20 01:33:35 -08:00
Ross Thompson
67e0b021ae several options for pcnextf on fence.i 2022-12-19 23:33:12 -06:00
Ross Thompson
d18ef45c18 More bp/ifu pcmux cleanup. 2022-12-19 23:16:58 -06:00
Ross Thompson
761cf54dcc Moved more muxes inside bp. 2022-12-19 22:51:55 -06:00
Ross Thompson
0097c166d6 Begin cleanup of ifu. partial move of pc muxes inside bp. 2022-12-19 22:46:11 -06:00
David Harris
954051da13 Removed CSR support from rv32i 2022-12-19 16:15:12 -08:00
David Harris
2393915bf2 Simplified InstrRawD register 2022-12-19 15:18:42 -08:00
David Harris
aac4b55b59 Explained hazard causes 2022-12-19 09:41:41 -08:00
David Harris
16b8fbbd2d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-12-19 09:09:57 -08:00
David Harris
b5958b1e11 Properly decode fcvtint to prevent unnecessary stalls 2022-12-19 09:09:48 -08:00
Ross Thompson
ddde82f928 Renamed FStallD to FPUStallD. 2022-12-19 09:28:45 -06:00
Alessandro Maiuolo
13c9f2e4a5 Added NumZeroE, AZeroM, and BZeroM 2022-12-18 20:02:40 -08:00
Alessandro Maiuolo
3bcb42adb6 fixed LOGRK. FIxed Xs in WC and WS from muxes reliant on SqrtE. note not linting on 4 copies radix 4 because IntBits only 7 bits wide (need 8) 2022-12-18 19:04:36 -08:00
Ross Thompson
c3b77926d5 I think I finally fixed a long hidden bug in the replacement policy. The figures in the textbook are correct. There was small bug in the rtl. 2022-12-18 18:30:35 -06:00
Ross Thompson
7a352edf13 Attempted to make a cache test. 2022-12-18 17:15:08 -06:00
Ross Thompson
9d1cb9337e Updated tests for fpga and BP. 2022-12-18 16:24:26 -06:00
Ross Thompson
5acdf541b9 Finally fixed the lru bug. It was actually a flush bug all along. At the end of flush writeback FlushAdr is incremented so clearly the dirty bit then clears the wrong set. Must either take an additional cycle to clear dirty and then change the address or clear the dirty bit before the cache bus acknowledgment. Changed it to clear at begining of that line's writeback before actually writting back. 2022-12-17 23:47:49 -06:00
Ross Thompson
9849983348 At long last found the subtle bug in the LRU. 
Since the LRU memory is two ports, 1 read and 1 write, a write in cycle 1 to address x should not
forward data to a read from address y in cycle 2.
A read form address x in cycle 2 would still require forwarding.
 2022-12-17 10:03:08 -06:00
Ross Thompson
c985988867 Fixed a bug with the new cache flush changes. 2022-12-16 19:28:32 -06:00
Ross Thompson
9b9e954cc5 Cleanup comments. 2022-12-16 17:08:35 -06:00
Ross Thompson
5f556817c7 Further cleanfsm cleanup. 2022-12-16 16:37:45 -06:00
Ross Thompson
493b1a4280 More cachefsm cache flush cleanup. 2022-12-16 16:32:21 -06:00
Ross Thompson
3132246a46 Oups found a bug with the new flush cache states. 2022-12-16 16:22:40 -06:00
Ross Thompson
698ca7d482 Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2022-12-16 15:37:03 -06:00
Ross Thompson
91e64a0d67 Cleanup of cache flush fsm enhancement. 2022-12-16 15:36:53 -06:00
Ross Thompson
ab3c5a0ca7 Rough draft of cache flush fsm enhancement. 2022-12-16 15:28:22 -06:00
cturek
0ceecd9961 Added integer support for initC 2022-12-16 19:02:11 +00:00
Ross Thompson
9c67972b21 Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2022-12-16 12:52:22 -06:00
Ross Thompson
f04ca5cb6a Fixed regression-wally to correct remove and mkdir wkdir. 2022-12-16 12:51:21 -06:00
cturek
9340a5eb49 Added mux for integer special case, renamed signals to match pipelined stage 2022-12-16 18:43:49 +00:00
David Harris
940fd2f924 Clean up interrupt masking by Commit 2022-12-16 08:27:39 -08:00
David Harris
a285f289a6 Disabled starting FPU divider when IDIV_ON_FPU = 0 2022-12-16 06:35:29 -08:00
cturek
9f1aa7ad19 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-12-16 03:41:39 +00:00
David Harris
da2d68c699 Use FlushE to reset integer divider FSM 2022-12-15 11:00:54 -08:00
David Harris
a8126458f6 Refactored stalls and flushes, including FDIV flush with FlushE 2022-12-15 10:56:18 -08:00
David Harris
97a432570a Regression delete wkdir files to prevent spurious failures 2022-12-15 10:24:58 -08:00
David Harris
3bef12b108 Renamed DIV_BITSPERCYCLE to IDIV_BITSPERCYCLE 2022-12-15 08:23:34 -08:00
Ross Thompson
8cd6a74c8f Hazard cleanup. 2022-12-15 10:05:17 -06:00
Ross Thompson
c253b882be Reworked the hazards to eliminate StallFCause. Flush and CSRWrites now flush F,D,E stages and set the correct PCNextF in the M stage. 2022-12-15 09:53:35 -06:00
Ross Thompson
0358a8d255 Merge branch 'main' into hazards 2022-12-15 08:44:59 -06:00
David Harris
e80e84aace Added IDIV_ON_FPU flag to control whether integer division uses FPU 2022-12-15 06:37:55 -08:00
David Harris
643a2e7cf9 Use FPU divider for integer division when F is supported 2022-12-14 17:03:13 -08:00
cturek
482caec42d Fixed BZero and initU/initUM muxes 2022-12-14 16:44:46 +00:00
Ross Thompson
4a0e4aed99 Signal renames to reflect figures. 2022-12-14 09:49:15 -06:00
Ross Thompson
8f04f2d9e7 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-12-14 09:34:34 -06:00
Ross Thompson
b69aa39f30 Reduced complexity of linebytemask. 2022-12-14 09:34:29 -06:00
cturek
e4c1bb2bff Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-12-14 15:13:44 +00:00
Ross Thompson
0f0fed2496 Broken dont' use. 2022-12-11 23:24:01 -06:00
Ross Thompson
dbc3dac03d Removed unused flushf. 2022-12-11 16:28:11 -06:00
Ross Thompson
ad7dd56180 Renamed CPUBusy to GatedStallF in IFU. 2022-12-11 15:54:19 -06:00
Ross Thompson
5b38b4e639 Renamed CPUBusy in LSU. 2022-12-11 15:52:51 -06:00
Ross Thompson
6d573b32d2 Changed CPUBusy to Stall in ebu modules. 2022-12-11 15:51:35 -06:00
Ross Thompson
232f866ad1 Renamed CPUBusy to Stall in cache. 2022-12-11 15:49:34 -06:00
Ross Thompson
a58fbd618e Moved CPUBusy out of HPTW. 2022-12-11 15:48:00 -06:00
cturek
930fcbe956 Fixed D sizing issues across fdivsqrt. Fixed preproc to accept either int or float inputs 2022-12-10 21:56:35 +00:00
Ross Thompson
d3b2e331c2 Added comments about why it is not possible to use FlushWay and VictimWay directly. 2022-12-09 17:07:35 -06:00
Ross Thompson
f09b9e1572 Finished merge of kip and ross's ifu fix. 2022-12-09 16:52:22 -06:00
Ross Thompson
981ac3963a Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-12-09 16:42:16 -06:00
Ross Thompson
1a24e7029f Minor simplification of cacheway way selection muxes. 2022-12-09 16:42:05 -06:00
Kip Macsai-Goren
055ca9ee37 Addded fix for 32 bit periph test and added test to regression 2022-12-06 09:56:08 -08:00
Ross Thompson
9dd0d66ab5 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-12-06 10:38:14 -06:00
Ross Thompson
5dbcf8fb10 Fixed bug Kip found. 
The no cache and no bus versions lacked assignment of CacheCommittedF in the IFU.
 2022-12-06 10:37:45 -06:00
Kip Macsai-Goren
55627f40e2 added passing GPIO test to 64 bit tests 2022-12-05 21:31:00 -08:00
Kip Macsai-Goren
c6662933c4 commented out periph test from wally32 periph so rv32ic doesn't hang 2022-12-05 20:23:16 -08:00
Kip Macsai-Goren
4e2f4855e6 added passing tests to regression 2022-12-05 20:16:02 -08:00
Kip Macsai-Goren
540d6c2f41 added -01 to all WALLY tests 2022-12-05 20:16:02 -08:00
Ross Thompson
1a9c932157 Renamed SelBusBuffer to SelFetchBuffer. 2022-12-05 17:51:13 -06:00
Ross Thompson
92066f81b6 Removed commented code. 2022-12-05 17:21:56 -06:00
Ross Thompson
37551ecc43 Renamed VictimTag to just Tag. Tag is used for both the victim and flush tags. 2022-12-05 17:19:51 -06:00
Ross Thompson
dc31add951 Cache signal renames. 2022-12-04 16:09:09 -06:00
Ross Thompson
9bf0eedf73 Optimized way selection logic. 2022-12-04 12:30:56 -06:00
Ross Thompson
a130a96b45 Found possible optimization as the way selection is shared in cache, cacheway, and cachelru. 2022-12-04 01:20:51 -06:00
Ross Thompson
3dea04e644 Moved selectedway mux into cacheway. It makes way more sense there. 2022-12-04 01:15:47 -06:00
Ross Thompson
f557150cae Rename LineByteMux to FetchbufferbyteSel. 2022-12-04 01:00:04 -06:00
Ross Thompson
fc05e27416 Updated riscv arch test removed misaligned1. 2022-12-04 00:18:10 +00:00
Ross Thompson
350fdd944d Revert "Changed weird D sizing. Better names in preproc. Finalized Int/Float input to divider." 
This reverts commit fb221d7b64.
 2022-12-04 00:01:58 +00:00
cturek
fb221d7b64 Changed weird D sizing. Better names in preproc. Finalized Int/Float input to divider. 2022-12-02 21:44:29 +00:00
cturek
04ac350a29 Added flops to preproc 2022-12-02 20:31:08 +00:00
David Harris
3a07d56d33 Renamed FPUStallD to FCvtIntStallD 2022-12-02 11:55:23 -08:00
David Harris
1b0f878c16 Renamed DivStartE to IFDivStartE 2022-12-02 11:30:49 -08:00
David Harris
db5f3c15a4 FPU divider working with execute stage stall 2022-12-02 11:11:53 -08:00
David Harris
a86c9de36b Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-12-02 04:28:50 -08:00
David Harris
6079a01bc8 update test list 2022-12-02 04:28:47 -08:00
Ross Thompson
602d191580 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-12-01 22:36:07 -06:00
David Harris
7c3e8553d1 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-12-01 16:27:36 -08:00
David Harris
0d23ab3ec1 reorder tests 2022-12-01 16:27:33 -08:00
Ross Thompson
3442b04f9e Properly flush cacheLRU. 2022-12-01 17:32:58 -06:00
David Harris
3a8602523e FPU test list 2022-12-01 10:18:36 -08:00
Ross Thompson
e403800ce8 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-12-01 11:47:54 -06:00
Ross Thompson
5025664cb0 Removed unused port on cacheway. 2022-12-01 11:47:48 -06:00
David Harris
28996d0b12 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-12-01 08:15:51 -08:00
David Harris
1bd639be6d code cleanup 2022-12-01 08:15:48 -08:00
Ross Thompson
e6bd86f4fa Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-11-30 17:19:04 -06:00
David Harris
4ddc8fd603 signal sufixes in integer division 2022-11-30 15:15:37 -08:00
Ross Thompson
fa22484cfe Reverted the IROM/DTIM address range modelsim assignment. 2022-11-30 17:13:33 -06:00
Ross Thompson
2f582cd91f Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-11-30 13:30:37 -06:00
Ross Thompson
a6355b1dcb More optimization. 2022-11-30 11:26:48 -06:00
Ross Thompson
0aa7ce0b24 Removed reset on dirty cache bits. 2022-11-30 11:04:37 -06:00
Ross Thompson
cedb234013 Turns out the merge of dirty and tag bits is complicated by the need to have byte write enables rather than bit write enables. Putting on hold for now. 2022-11-30 11:01:25 -06:00
Ross Thompson
0454eb95ad Preparing to merge dirty and tag srams. 2022-11-30 10:40:48 -06:00
Ross Thompson
de538d1c2f Intermediate commit. Replaced flip flop dirty bit array with sram. 2022-11-30 00:08:31 -06:00
cturek
10c2d45888 div tests in sim-wally 2022-11-30 02:32:04 +00:00
Ross Thompson
453ea36512 Optimization of cacheway. 2022-11-29 18:30:47 -06:00
Ross Thompson
fbf543bf57 Updated HPTW to route access faults generated by the HPTW to the original access type either instruction access fault, load access fault or store access fault. 2022-11-29 17:19:31 -06:00
Ross Thompson
0277227323 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-11-29 14:57:38 -06:00
Ross Thompson
b5718c9baa Fixed a bug with the replacement policy. It was updating the wrong set on load hits. 2022-11-29 14:51:09 -06:00
Ross Thompson
96cc4c7ebe Cleaned up the wavefile and added logic to linearly populate the LRU before all ways are filled. 2022-11-29 14:09:48 -06:00
Kip Macsai-Goren
c7c578c104 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-11-29 10:43:44 -08:00
Kip Macsai-Goren
44ea8d8b22 added failing satp invalid tests to regression 2022-11-29 10:43:38 -08:00
Ross Thompson
78acd40424 Renamed signals in the cache. 2022-11-29 10:52:40 -06:00
Ross Thompson
6dd5668d21 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-11-22 18:07:32 -06:00
cturek
bdb9e24a66 Almost done with Int division 2022-11-22 22:22:59 +00:00
cturek
78c2ce5649 Updated testbench/wave for fdivsqrt new start signals 2022-11-22 22:22:26 +00:00
Ross Thompson
279f5bc615 Cleanup cacheLRU. 2022-11-22 14:59:01 -06:00
Ross Thompson
e1dbe58632 File name change for cachereplacement policy to cacheLRU 2022-11-20 22:35:02 -06:00
Ross Thompson
4e926ba4cf Signal name changes for LRU. 2022-11-20 22:31:36 -06:00
Ross Thompson
00218d559f Missing a file. Last commit will fail. 2022-11-17 17:45:41 -06:00
Ross Thompson
0106777f02 Finally have the correct replacement policy implementation. 2022-11-17 17:36:37 -06:00
Ross Thompson
faa13a96e0 I found the issue with the cache changes. FlushW is not asserted for all TrapM. Ecall and Ebreak don't flush the W stage. However the ifu's bus controllable must disable the BusRW for all traps. 2022-11-16 15:38:37 -06:00
Ross Thompson
22ad49eef2 Progress on the cache replacement policy implementation. 2022-11-16 15:35:34 -06:00
Ross Thompson
0796cd92fc Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-11-16 12:42:29 -06:00
Ross Thompson
42111db671 Oups found a bug with my cache changes. I took TrapM out of the logic path for selecting the cache's address CAdr (previously RAdr) to improve the critical path. This is fine for the dcache because both the E and M stages are flushed. However for the ICache only F is flushed. PCNextF is valid and points to XTVEC so the cache must take NextAdr rather than PAdr as CAdr. 2022-11-16 12:36:58 -06:00
David Harris
59335ac70f comment cleanup 2022-11-16 10:23:20 -08:00
David Harris
be9c618c94 Renamed DivBusy to FDivBusyE in FPU 2022-11-16 10:13:27 -08:00
David Harris
128cc86254 Moved DivStartE to fdivsqrtfsm 2022-11-16 10:00:07 -08:00
Ross Thompson
1f21a2bab1 Created improved cache replacement policy implementation. This version is generic and works for any number of ways. Not fully tested and is currently commented out. 2022-11-16 11:15:34 -06:00
cturek
ffd03e9548 Attempt to fix FPGA synth errors 2022-11-15 20:34:28 +00:00
cturek
98b66aab9f Fixed lint errors in postprocessing 2022-11-15 20:31:23 +00:00
Ross Thompson
3df51716b1 Fixed a bug with the hptw configuration not correctly avoiding UPDATE_PTE state. 2022-11-14 16:02:20 -06:00
Ross Thompson
b53f8eceef Renamed Flush to FlushStage in the cache. 2022-11-14 14:11:05 -06:00
Ross Thompson
284b97aff6 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-11-14 13:48:56 -06:00
David Harris
6372139af4 Removed comment about nonexistent possible bug 2022-11-14 09:56:33 -08:00
David Harris
06dbed92c8 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-11-14 09:52:24 -08:00
David Harris
f9202187ba Removed comment about nonexistent possible bug 2022-11-14 09:52:21 -08:00
Ross Thompson
13e6f7d80b Changed names of cache signals. 2022-11-13 21:36:12 -06:00
Ross Thompson
788ae5fb18 Updated wave file. 2022-11-13 21:34:45 -06:00
cturek
abaa33b92a Added majority of combinational logic 2022-11-14 00:06:38 +00:00
cturek
6740d77b63 Added Quotient/Remainder calcs to normal termination 2022-11-13 23:44:34 +00:00
cturek
12e3646153 Added flops for n and m, added B=0 signal 2022-11-13 23:02:43 +00:00
cturek
f10700e666 Added A<B signal to fdivsqrt, started postprocessing merge 2022-11-13 22:40:26 +00:00
Ross Thompson
9d7ba19fe1 Changed IMWriteDataM to IHWriteDataM. 2022-11-13 12:27:48 -06:00
Ross Thompson
421c6f9c48 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 
hazard was not a straight forward merge.  I changed the way the LSU and IFU generate IFUStallF and LSUStallM.  They need to be suppressed by TrapM now.
 2022-11-13 12:25:22 -06:00
David Harris
84c4558641 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-11-13 04:23:26 -08:00
David Harris
879e62912b HPTW cleanup 2022-11-13 04:23:23 -08:00
David Harris
2ebdfa3f68 Comments about division hazards 2022-11-13 04:17:37 -08:00
Ross Thompson
54544ae251 Moved all remaining bus logic from the LSU into ahbcacheinterface. 2022-11-11 14:30:32 -06:00
cturek
4a8661649c Added integer step counter to fsm 2022-11-11 00:23:25 +00:00
Ross Thompson
c028306ba3 Fixed name change in hptw. 2022-11-10 16:13:31 -06:00
Ross Thompson
d912981ec9 Wavefile update. 2022-11-10 15:48:06 -06:00
Ross Thompson
40367eaf45 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-11-10 15:46:25 -06:00
Ross Thompson
8658a25218 Renamed Word to Beat for ahbcacheinterface. 2022-11-09 17:52:50 -06:00
Ross Thompson
028e2b0f91 Renamed CACHE_EVICT to CACHE_WRITEBACK. 2022-11-09 17:43:06 -06:00
cturek
9d30a832c3 Reoredered tests for arch32m 2022-11-09 18:42:00 +00:00
cturek
b723e16893 Fixed asign and bsign 2022-11-09 18:41:26 +00:00
Ross Thompson
be8e0eee1b Removed TrapM from the LSU and IFU. TrapM is replaced with FlushW for both. (Don't like this for the IFU). 
FlushW prevents writting the cache, dtim, and bus state.  FlushW still gates HTRANS.
FlushW does not impact the mealy outputs of the cache and bus FSMs and hazard is updated to
not stall W if we get a trap.
 2022-11-07 15:50:55 -06:00
David Harris
f7b94c12fc Moved lsuvirtmem muxes into hptw 2022-11-07 11:13:34 -08:00
Ross Thompson
d4f4950d2c Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-11-07 09:10:51 -06:00
cturek
d571b5f9a5 propagated otfc swap to Rad2 and 4 qslc 2022-11-06 23:32:38 +00:00
Ross Thompson
e7d24609cd Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-11-06 17:22:25 -06:00
cturek
54f09f3616 Added conditional OTFC swap for simplified int postprocessing 2022-11-06 23:09:09 +00:00
cturek
c3e635c788 Finished Int Preprocessinggit add ../src/fpu/fdivsqrt/fdivsqrtpreproc.sv 2022-11-06 22:40:21 +00:00
cturek
a49ea2a16d Added n and rightshiftx 2022-11-06 22:31:48 +00:00
cturek
350d4d254f p calculation 2022-11-06 22:24:21 +00:00
cturek
83051a5351 Changed lzc names, started int/fp size merge in preproc 2022-11-06 22:21:35 +00:00
cturek
2cbe2fd70b Added n, p, and m signals between fdivsqrt submodules. Added w64 and mdue to divsqrt testbench. 2022-11-06 22:08:18 +00:00
cturek
6bc4c1318e Added new macros for int div preprocessing, added p, n, and rightshiftx logic 2022-11-06 21:53:48 +00:00
David Harris
53a88fec8f Reorder embench tests to prevent crash 2022-11-04 15:21:51 -07:00
David Harris
60cfa0d69c HPTW cleanup 2022-11-04 15:21:09 -07:00
Ross Thompson
44ee31a7f6 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-11-04 13:30:08 -05:00
cturek
06a9305766 renamed remOp to RemOp 2022-11-03 22:37:25 +00:00
cturek
e37f564e84 Added rem/div operation to postprocessor 2022-11-02 17:49:40 +00:00
Ross Thompson
44171c342d Reduced complexity of logic supressing cache operations. 2022-11-01 15:23:24 -05:00
cturek
e8d7607e87 Added buffered signals for int/fp 2022-10-28 21:47:24 +00:00
cturek
9f41e57f03 Config Cleanup 2022-10-27 22:38:56 +00:00
Ross Thompson
dc3a9f2342 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-10-26 14:48:50 -05:00
Ross Thompson
403434580d Fixed the uart transmit fifo overrun bug. 2022-10-26 14:48:09 -05:00
cturek
7301fc7f18 small signal cleanup 2022-10-26 18:42:49 +00:00
cturek
6caf7bb7e2 abs for int inputs 2022-10-26 16:18:05 +00:00
cturek
ec4646b412 Added signed division to fdivsqrt 2022-10-26 16:13:41 +00:00
cturek
71d16eacef unbroke DIVb 2022-10-26 16:11:51 +00:00
cturek
1febdb75b7 Config cleanup 2022-10-25 21:04:09 +00:00
Jacob Pease
160ca366c8 Added PLIC signals for debugging on FPGA. 2022-10-25 13:57:09 -05:00
cturek
ff7d6b2932 Started Integer Preprocessing 2022-10-25 17:48:43 +00:00
Ross Thompson
9ba487c323 Setup to run with both the vcu108 and vcu118 boards. Set the parameters in the Makefile. 2022-10-24 15:38:39 -05:00
Ross Thompson
7244ca1e7b Bit width error. 2022-10-24 13:48:47 -05:00
Ross Thompson
51408c620e Found a way to remove the interlock fsm. Dramatically reducing the complexity of virtual memory and page table walks. 2022-10-23 13:46:50 -05:00
Ross Thompson
775309165b Small cleanup of interlockfsm. 2022-10-22 16:29:51 -05:00
Ross Thompson
a59df0c77d Created one off test to replicate the floating point forwarding hazard bug. 2022-10-22 16:29:12 -05:00
Ross Thompson
6696624971 comment updates. 2022-10-22 16:28:44 -05:00
Ross Thompson
12c5525807 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-10-22 16:27:30 -05:00
Ross Thompson
4db912678d Changed FDivBusyE to stall the whole pipeline. Any instruction in the Executation which depended on the output of an instruction in the writeback stage would be lost if the back end of the pipelined advanced. The solution is to stall the whole pipeline. 2022-10-22 16:27:20 -05:00
Jacob Pease
b1170ec7a2 Extended rxfifotimeout count to actually be 4 characters long. 2022-10-20 17:35:49 -05:00
Ross Thompson
2c5847b01f Moving interlockfsm changes to a temporary branch. 
reduced complexity of cache mux controls.
 2022-10-19 15:08:23 -05:00
Ross Thompson
9cadd4c6ec Broken don't use this state. 2022-10-19 14:31:22 -05:00
Ross Thompson
c6a9b17918 Noted possible bug with endianness during hptw. 
Minor complexity reduction in interlockfsm.  I think there is a lot of room to simplify.
 2022-10-19 12:20:19 -05:00
Ross Thompson
a53ca5c99f Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-10-19 10:42:31 -05:00
Ross Thompson
d6f907f444 Sort of solved the bit width warning for dtim, irom ranges. 2022-10-19 10:42:19 -05:00
Ross Thompson
d4c5440f25 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-10-18 15:06:09 -05:00
Ross Thompson
92accfb1a6 Updated uart settings and fpga wave config. 2022-10-18 15:05:33 -05:00
Ross Thompson
47608df73e Possible fix for interrupt during a floating point divide. 2022-10-18 15:04:21 -05:00
Ross Thompson
65c2fe294a Merged cacheable with seluncachedadr. 2022-10-17 13:29:21 -05:00
David Harris
aa5fe52407 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-10-14 17:33:36 -07:00
David Harris
51b702fa17 Removed unused FPU waves 2022-10-14 17:33:32 -07:00
amaiuolo
56455bb9ad Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-10-13 22:36:57 +00:00
amaiuolo
1ae48e0edc added amaiuolo@hmc.edu 2022-10-13 22:36:52 +00:00
Ross Thompson
22603464ae Fixed uncached read bug introduced by yesterday's changes. 2022-10-13 11:11:36 -05:00
Ross Thompson
a4390dd07f Fixed LSU to correctly handle the difference between LLEN and AHBW. 2022-10-12 12:06:15 -05:00
Ross Thompson
b79872180b Actually fixed the bus width issue coming out of the cache. 
The root cause is the ahb bus width can be different from LLEN.
If we switch the d-cache to outputing LLEN and on LLEN intervals, subword read needs to operate on LLEN as well.
Then the cache always outputs LLEN data which may need to be muxed down into 2 or more subwords if ABHW is smaller than LLEN.
 2022-10-12 11:33:10 -05:00
Kip Macsai-Goren
1dd9cb6697 quick fix to endianness wapping 64 bit reads in 32 bit confgs 2022-10-11 23:08:02 +00:00
Ross Thompson
7ddcf38fa9 Modified LSU to support DTIM without CSRs. 2022-10-11 14:05:20 -05:00
Ross Thompson
77de96905a Fixed first problem with the rv64i IROM. 2022-10-11 11:35:40 -05:00
Ross Thompson
dfd07a57fd Modified the do scripts to change the DTIM_RANGE and IROM_RANGE to large values from the defaults. 
The defaults are used for synthesis.
rv64i and rv32i: DTIM 2KiB, IROM 2KiB
rv32ic: DTIM 4KiB, IROM 16KiB
Regression tests require 8MiB or larger so modelsim overrides.
 2022-10-11 10:47:13 -05:00
David Harris
cc9a2fc62d Removed imperas tests from rv32i/rv64i because the configs lack privileged support expected in the tests. Also cleaned up comment in LSU 2022-10-10 10:22:12 -07:00
David Harris
31e9af0eb2 Made simple RV64 configuration be RV64i. Eliminated rv64ic and rv64fp. Fixed some bugs related to new width 2022-10-10 09:10:55 -07:00
David Harris
fde4832642 Removed unnecessary configuration conditions from subwordread sign extension/NaN boxing 2022-10-10 07:12:37 -07:00
Ross Thompson
4bf5245f75 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-10-09 16:46:51 -05:00
Ross Thompson
9d23b0e6d6 Reorganized the configs. 2022-10-09 16:46:48 -05:00
David Harris
04dc0ac02c New fdivsqrtqsel4cmp module based on comparators rather than table lookup 2022-10-09 04:47:44 -07:00
David Harris
4f312ea2e7 Moved shift into divsqrt stage and cleaned up comments 2022-10-09 04:45:45 -07:00
David Harris
2aa43848f5 fdivsqrt code cleanup 2022-10-09 03:37:27 -07:00
Ross Thompson
6ff4abd4f7 Cleaned up the new muxes to select between IROM/ICACHE/BUS and DTIM/DCACHE/BUS. 2022-10-05 15:46:53 -05:00
Ross Thompson
28584e4cca Fixed wally32e. 2022-10-05 15:37:01 -05:00
Ross Thompson
52a1d3dafe Name clarifications. 2022-10-05 15:36:56 -05:00
Ross Thompson
aa09b1ef16 Fixed bug with combined dtim+bus. 2022-10-05 15:16:01 -05:00
Ross Thompson
98521d073f Possibly have working dtim + bus config. 2022-10-05 15:08:20 -05:00
Ross Thompson
b01ee070bd Updated wavefile. 2022-10-05 14:55:40 -05:00
Ross Thompson
bf6f0e7219 Fixed bug in EBU. 2022-10-05 14:51:12 -05:00
Ross Thompson
cabcb5e89e Modified the LSU and IFU to allow concurrent DTIM/DCACHE+BUS and IROM/ICACHE+BUS. 
Don't use this commit as the rv32i tests are not passing.
 2022-10-05 14:51:02 -05:00
Ross Thompson
5e09d1cca7 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-10-05 14:03:44 -05:00
David Harris
29033dc334 Changed RV32i config to use DTIM and bus. Don't use this commit - it will break rv32i tests. 2022-10-05 11:46:52 -07:00
Ross Thompson
ea70e1c598 Optimized the ebu's beat counting. 2022-10-05 10:58:23 -05:00
Ross Thompson
294645a49f Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-10-04 17:38:49 -05:00
Ross Thompson
494f8b94f4 Reordered the eviction and fetch in cache so it follows a more logical order. 2022-10-04 17:36:07 -05:00
Ross Thompson
18e739befc Modified cache lru to not have the delayed write. 2022-10-04 15:14:58 -05:00
Kip Macsai-Goren
c18c181fc0 fixed endianness mstatush problem, passes make, not regression 2022-10-04 17:37:39 +00:00
Kip Macsai-Goren
3f6d05f7a2 addded renamed file 2022-10-04 17:37:05 +00:00
Kip Macsai-Goren
9a0b98037b Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2022-10-04 17:33:54 +00:00
Kip Macsai-Goren
fb464b9546 Renamed endianswap to match module name 2022-10-04 17:33:49 +00:00
Ross Thompson
0ed0c18aa1 Fixed a very subtle bug in the trap handler. It was possible to select the wrong cause if an interrupt was pending, but it was supressed by Committed and another exception triggered. 2022-10-02 16:21:21 -05:00
Ross Thompson
d08c29e3c5 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-10-01 15:01:22 -05:00
Ross Thompson
41ab4850e1 Disable IFU bus access on TrapM. 2022-10-01 14:54:16 -05:00
Ross Thompson
e27fcb1577 Added logic to not implement the save/restore muxes for LSU in the EBU's controller input stage. 2022-09-29 18:37:34 -05:00
David Harris
657f16dfd1 Adding start signals for integer divider to fdivsqrt 2022-09-29 16:30:25 -07:00
Ross Thompson
2c0132aa9c Renamed signals in EBU. 2022-09-29 18:29:38 -05:00
cturek
e8a869e0e7 Added integer inputs and flags to divsqrt 2022-09-29 23:08:27 +00:00
Ross Thompson
58d597b614 Simplification to EBU. 2022-09-29 18:06:34 -05:00
Ross Thompson
d81af3bca8 Fixed HTRANS not changing after accepting HREADY. This exposed a bug in uncore. 2022-09-29 11:54:03 -05:00
Ross Thompson
32449dfe97 Hmm. the icache and ifu didn't have a CommittedF signals going back to the privileged unit. They probably should. If an interrupt occurred during the middle of an instruction fetch icache miss I think it would corrupt the icache. 2022-09-28 17:39:51 -05:00
Ross Thompson
4db017dac3 Possible fix for ifu/lsu arbiration issue. 2022-09-27 17:24:35 -05:00
Ross Thompson
4062fe56c0 Possible fix to the bus cache interaction. 2022-09-27 11:34:33 -05:00
Ross Thompson
07bb11518e Found a hidden bug in the cache to bus fsm interlock. 2022-09-26 17:41:30 -05:00
Ross Thompson
996c4ca8f2 renamed ahbmulticontroller to ebu. 2022-09-26 14:37:18 -05:00
Ross Thompson
8ed173a5f5 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-09-26 12:49:16 -05:00
Ross Thompson
0fcc314d06 Yesterday David and I found what is likely a bug in our AHB implementation. HTRANS was getting reset to 2 rather than 0 at the end of a burst transaction. This is fixed. 2022-09-26 12:48:26 -05:00