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Clean up interrupt masking by Commit

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This commit is contained in:
David Harris 2022-12-16 08:27:39 -08:00
parent a285f289a6
commit 940fd2f924
1 changed files with 4 additions and 3 deletions
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7
pipelined/src/privileged/trap.sv
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@ -53,7 +53,7 @@ module trap (
logic Committed;
logic BothInstrAccessFaultM;
(* mark_debug = "true" *) logic [11:0] PendingIntsM, ValidIntsM;
(* mark_debug = "true" *) logic [11:0] PendingIntsM, ValidIntsM, EnabledIntsM;
///////////////////////////////////////////
// Determine pending enabled interrupts
@ -66,8 +66,9 @@ module trap (
assign PendingIntsM = MIP_REGW & MIE_REGW;
assign IntPendingM = |PendingIntsM;
assign Committed = CommittedM | CommittedF;
assign ValidIntsM = {12{~Committed}} & ({12{MIntGlobalEnM}} & PendingIntsM & ~MIDELEG_REGW | {12{SIntGlobalEnM}} & PendingIntsM & MIDELEG_REGW);
assign InterruptM = (|ValidIntsM) && InstrValidM && ~Committed; // suppress interrupt if the memory system has partially processed a request.
assign EnabledIntsM = ({12{MIntGlobalEnM}} & PendingIntsM & ~MIDELEG_REGW | {12{SIntGlobalEnM}} & PendingIntsM & MIDELEG_REGW);
assign ValidIntsM = {12{~Committed}} & EnabledIntsM;
assign InterruptM = (|ValidIntsM) && InstrValidM; // suppress interrupt if the memory system has partially processed a request.
assign DelegateM = `S_SUPPORTED & (InterruptM ? MIDELEG_REGW[CauseM[3:0]] : MEDELEG_REGW[CauseM]) &
(PrivilegeModeW == `U_MODE | PrivilegeModeW == `S_MODE);