Ross Thompson c253b882be Reworked the hazards to eliminate StallFCause. Flush and CSRWrites now flush F,D,E stages and set the correct PCNextF in the M stage.		2022-12-15 09:53:35 -06:00
..
config	Added IDIV_ON_FPU flag to control whether integer division uses FPU	2022-12-15 06:37:55 -08:00
misc	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00
regression	FPU test list	2022-12-01 10:18:36 -08:00
src	Reworked the hazards to eliminate StallFCause. Flush and CSRWrites now flush F,D,E stages and set the correct PCNextF in the M stage.	2022-12-15 09:53:35 -06:00
testbench	Fixed D sizing issues across fdivsqrt. Fixed preproc to accept either int or float inputs	2022-12-10 21:56:35 +00:00