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Removed unused FPU signals
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@ -37,9 +37,7 @@ module fma(
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input logic XZero, YZero, ZZero, // is the input zero
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input logic [2:0] OpCtrl, // 000 = fmadd (X*Y)+Z, 001 = fmsub (X*Y)-Z, 010 = fnmsub -(X*Y)+Z, 011 = fnmadd -(X*Y)-Z, 100 = fmul (X*Y)
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input logic [`FMTBITS-1:0] Fmt, // format of the result single double half or quad
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output logic [`NE+1:0] Pe, // the product's exponent B(NE+2.0) format; adds 2 bits to allow for size of number and negative sign
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output logic ZmSticky, // sticky bit that is calculated during alignment
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output logic KillProd, // set the product to zero before addition if the product is too small to matter
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output logic [3*`NF+5:0] Sm, // the positive sum's significand
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output logic InvA, // Was A inverted for effective subtraction (P-A or -P+A)
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output logic As, // the aligned addend's sign (modified Z sign for other opperations)
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@ -47,12 +45,15 @@ module fma(
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output logic Ss, // the sum's sign
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output logic [`NE+1:0] Se,
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output logic [$clog2(3*`NF+7)-1:0] SCnt // normalization shift count
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);
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);
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logic [2*`NF+1:0] Pm; // the product's significand in U(2.2Nf) format
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logic [3*`NF+5:0] Am; // addend aligned's mantissa for addition in U(NF+5.2NF+1)
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logic [3*`NF+5:0] AmInv; // aligned addend's mantissa possibly inverted
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logic [2*`NF+1:0] PmKilled; // the product's mantissa possibly killed
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logic KillProd; // set the product to zero before addition if the product is too small to matter
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logic [`NE+1:0] Pe; // the product's exponent B(NE+2.0) format; adds 2 bits to allow for size of number and negative sign
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///////////////////////////////////////////////////////////////////////////////
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// Calculate the product
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// - When multipliying two fp numbers, add the exponents
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@ -108,10 +108,8 @@ module fpu (
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// Fma Signals
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logic [3*`NF+5:0] SmE, SmM;
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logic [`NE+1:0] PeE, PeM;
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logic ZmStickyE, ZmStickyM;
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logic [`NE+1:0] SeE,SeM;
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logic KillProdE, KillProdM;
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logic InvAE, InvAM;
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logic AsE, AsM;
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logic PsE, PsM;
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@ -256,9 +254,9 @@ module fpu (
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.XZero(XZeroE), .YZero(YZeroE), .ZZero(ZZeroE),
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.OpCtrl(OpCtrlE), .Fmt(FmtE),
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.As(AsE), .Ps(PsE), .Ss(SsE), .Se(SeE),
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.Sm(SmE), .Pe(PeE),
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.Sm(SmE),
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.InvA(InvAE), .SCnt(SCntE),
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.ZmSticky(ZmStickyE), .KillProd(KillProdE));
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.ZmSticky(ZmStickyE));
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// divide and squareroot
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// - fdiv
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@ -353,10 +351,9 @@ module fpu (
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{XsM, YsM, XZeroM, YZeroM, ZZeroM, XInfM, YInfM, ZInfM, XNaNM, YNaNM, ZNaNM, XSNaNM, YSNaNM, ZSNaNM, ZDenormM});
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flopenrc #(1) EMRegCmpFlg (clk, reset, FlushM, ~StallM, PreNVE, PreNVM);
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flopenrc #(3*`NF+6) EMRegFma2(clk, reset, FlushM, ~StallM, SmE, SmM);
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flopenrc #(`NE+2) EMRegFma3(clk, reset, FlushM, ~StallM, PeE, PeM);
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flopenrc #($clog2(3*`NF+7)+8+`NE) EMRegFma4(clk, reset, FlushM, ~StallM,
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{ZmStickyE, KillProdE, InvAE, SCntE, AsE, PsE, SsE, SeE},
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{ZmStickyM, KillProdM, InvAM, SCntM, AsM, PsM, SsM, SeM});
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flopenrc #($clog2(3*`NF+7)+7+`NE) EMRegFma4(clk, reset, FlushM, ~StallM,
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{ZmStickyE, InvAE, SCntE, AsE, PsE, SsE, SeE},
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{ZmStickyM, InvAM, SCntM, AsM, PsM, SsM, SeM});
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flopenrc #(`NE+`LOGCVTLEN+`CVTLEN+4) EMRegCvt(clk, reset, FlushM, ~StallM,
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{CeE, CvtShiftAmtE, CvtResDenormUfE, CsE, IntZeroE, CvtLzcInE},
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{CeM, CvtShiftAmtM, CvtResDenormUfM, CsM, IntZeroM, CvtLzcInM});
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@ -375,8 +372,8 @@ module fpu (
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assign FpLoadStoreM = FResSelM[1];
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postprocess postprocess(.Xs(XsM), .Ys(YsM), .Ze(ZeM), .Xm(XmM), .Ym(YmM), .Zm(ZmM), .Frm(FrmM), .Fmt(FmtM), .FmaPe(PeM),
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.FmaZmS(ZmStickyM), .FmaKillProd(KillProdM), .XZero(XZeroM), .YZero(YZeroM), .ZZero(ZZeroM), .XInf(XInfM), .YInf(YInfM), .DivQm(QmM), .FmaSs(SsM),
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postprocess postprocess(.Xs(XsM), .Ys(YsM), .Ze(ZeM), .Xm(XmM), .Ym(YmM), .Zm(ZmM), .Frm(FrmM), .Fmt(FmtM),
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.FmaZmS(ZmStickyM), .XZero(XZeroM), .YZero(YZeroM), .ZZero(ZZeroM), .XInf(XInfM), .YInf(YInfM), .DivQm(QmM), .FmaSs(SsM),
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.ZInf(ZInfM), .XNaN(XNaNM), .YNaN(YNaNM), .ZNaN(ZNaNM), .XSNaN(XSNaNM), .YSNaN(YSNaNM), .ZSNaN(ZSNaNM), .FmaSm(SmM), .DivQe(QeM), /*.DivDone(DivDoneM), */
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.ZDenorm(ZDenormM), .FmaAs(AsM), .FmaPs(PsM), .OpCtrl(OpCtrlM), .FmaSCnt(SCntM), .FmaSe(SeM),
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.CvtCe(CeM), .CvtResDenormUf(CvtResDenormUfM),.CvtShiftAmt(CvtShiftAmtM), .CvtCs(CsM), .ToInt(FWriteIntM), .DivS(DivSM),
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@ -32,10 +32,8 @@
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module fmashiftcalc(
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input logic [3*`NF+5:0] FmaSm, // the positive sum
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input logic [`NE-1:0] Ze, // exponent of Z
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input logic [`NE+1:0] FmaPe, // X exponent + Y exponent - bias
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input logic [$clog2(3*`NF+7)-1:0] FmaSCnt, // normalization shift count
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input logic [`FMTBITS-1:0] Fmt, // precision 1 = double 0 = single
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input logic FmaKillProd, // is the product set to zero
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input logic [`NE+1:0] FmaSe,
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output logic [`NE+1:0] NormSumExp, // exponent of the normalized sum not taking into account denormal or zero results
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output logic FmaSZero, // is the result denormalized - calculated before LZA corection
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@ -48,10 +48,8 @@ module postprocess (
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input logic FmaAs, // the modified Z sign - depends on instruction
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input logic FmaPs, // the product's sign
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input logic [`NE+1:0] FmaSe,
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input logic [`NE+1:0] FmaPe, // Product exponent
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input logic [3*`NF+5:0] FmaSm, // the positive sum
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input logic FmaZmS, // sticky bit that is calculated during alignment
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input logic FmaKillProd, // set the product to zero before addition if the product is too small to matter
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input logic FmaSs,
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input logic [$clog2(3*`NF+7)-1:0] FmaSCnt, // the normalization shift count
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//divide signals
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@ -148,7 +146,7 @@ module postprocess (
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cvtshiftcalc cvtshiftcalc(.ToInt, .CvtCe, .CvtResDenormUf, .Xm, .CvtLzcIn,
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.XZero, .IntToFp, .OutFmt, .CvtResUf, .CvtShiftIn);
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fmashiftcalc fmashiftcalc(.FmaSm, .Ze, .FmaPe, .FmaSCnt, .Fmt, .FmaKillProd, .NormSumExp, .FmaSe,
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fmashiftcalc fmashiftcalc(.FmaSm, .Ze, .FmaSCnt, .Fmt, .NormSumExp, .FmaSe,
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.FmaSZero, .FmaPreResultDenorm, .FmaShiftAmt, .FmaShiftIn);
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divshiftcalc divshiftcalc(.Fmt, .Sqrt, .DivQe, .DivQm, .DivResDenorm, .DivDenormShiftPos, .DivShiftAmt, .DivShiftIn);
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