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Replaced || and && with single ops

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This commit is contained in:
David Harris 2022-12-20 01:33:35 -08:00
parent 67e0b021ae
commit 0c10ec942a
2 changed files with 2 additions and 2 deletions
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2
pipelined/src/privileged/privdec.sv
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@ -52,7 +52,7 @@ module privdec (
// Decode privileged instructions
///////////////////////////////////////////
assign sretM = PrivilegedM & (InstrM[31:20] == 12'b000100000010) & `S_SUPPORTED &
(PrivilegeModeW == `M_MODE || PrivilegeModeW == `S_MODE & ~STATUS_TSR);
(PrivilegeModeW == `M_MODE | PrivilegeModeW == `S_MODE & ~STATUS_TSR);
assign mretM = PrivilegedM & (InstrM[31:20] == 12'b001100000010) & (PrivilegeModeW == `M_MODE);
assign ecallM = PrivilegedM & (InstrM[31:20] == 12'b000000000000);
assign ebreakM = PrivilegedM & (InstrM[31:20] == 12'b000000000001);

2
pipelined/src/privileged/trap.sv
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@ -68,7 +68,7 @@ module trap (
assign Committed = CommittedM | CommittedF;
assign EnabledIntsM = ({12{MIntGlobalEnM}} & PendingIntsM & ~MIDELEG_REGW | {12{SIntGlobalEnM}} & PendingIntsM & MIDELEG_REGW);
assign ValidIntsM = {12{~Committed}} & EnabledIntsM;
assign InterruptM = (|ValidIntsM) && InstrValidM; // suppress interrupt if the memory system has partially processed a request.
assign InterruptM = (|ValidIntsM) & InstrValidM; // suppress interrupt if the memory system has partially processed a request.
assign DelegateM = `S_SUPPORTED & (InterruptM ? MIDELEG_REGW[CauseM[3:0]] : MEDELEG_REGW[CauseM]) &
(PrivilegeModeW == `U_MODE | PrivilegeModeW == `S_MODE);