Jacob Pease
2dc7e0f76f
Added and extra header and changed the comments to be accurate in ram1p1rwbe.sv
2024-08-06 17:36:42 -05:00
Jacob Pease
1e20d5aea6
Added preload pointing to data.mem in ram1p1rwbe.sv
2024-08-02 15:21:15 -05:00
Jacob Pease
336a413f31
Added ability to split boot.memfile into boot.mem and data.mem.
2024-07-25 11:19:15 -05:00
David Harris
8bae52b09d
Lint cleanup of unused signals
2024-06-18 06:49:17 -07:00
David Harris
7509e856df
Removed asynchronous reset causing lint issue in peripherals
2024-06-18 05:49:12 -07:00
David Harris
8f09240e6c
Simplified outdated documentation pointers
2024-06-14 03:42:15 -07:00
David Harris
b1c9450b4a
Code cleanup: RAM, fdivsqrt
2024-06-14 03:35:05 -07:00
David Harris
6789f32154
Starting code cleanup
2024-06-14 02:54:43 -07:00
David Harris
06e34b7be4
Fixed byte enables for synthesis
2024-04-27 06:25:24 -07:00
David Harris
235a3dcfca
ROM preload compatible with Verilator lint, sim, and Design Compiler
2024-04-24 08:44:37 -07:00
David Harris
cc236bdb25
Resolved merge conflicts
2024-04-22 12:16:06 -07:00
David Harris
3f195884e9
Defined bit sizes more precisely to help VCS lint and conform to coding style
2024-04-21 08:40:11 -07:00
David Harris
be15a11622
Fixed conflicts on getenv
2024-04-21 08:38:13 -07:00
David Harris
00a1c0fc57
Fixed WALLY/RISCV paths in testbench/rom1p1r; search log files for warnings and errors
2024-04-21 00:02:15 -07:00
David Harris
fd6a6b2249
environment variable cleanup
2024-04-20 22:52:08 -07:00
David Harris
338f37b570
Moved getenv/getenvval declaration to config-shared so lint and regression both run
2024-04-20 17:19:42 -07:00
slmnemo
f0229e970b
Fixed getenvvar verilator bug in rom1p1r, Removed unused system function from testbench.
2024-04-20 17:07:54 -07:00
Kunlin Han
08dd2eac74
Add getenvval for rom. Related to issue #723 .
2024-04-17 23:26:09 -07:00
Kunlin Han
22b59138f0
Remove all #delay from non-testbench.
2024-03-16 11:20:32 -07:00
Kunlin Han
8c67a76912
Remove all #delay from non-testbench.
2024-03-13 10:31:40 -07:00
David Harris
e0eb91f795
Changed always @(posedge clk) to always_ff @(posedge clk) where it was omitted in several places
2024-03-06 11:02:04 -08:00
David Harris
b386331cc8
Changed '0 to 0 where possible per Chapter 4 style guidelines
2024-03-06 05:48:17 -08:00
David Harris
45e2317636
Added Wally github address to header comments
2024-01-29 05:38:11 -08:00
Rose Thompson
5062a8c89c
Added parameter for cache's SRAM length.
...
Progress towards verilator support.
2023-12-18 12:50:49 -06:00
David Harris
ff26baf7e8
Rolled back attempt to support Verilator
2023-12-13 12:53:44 -08:00
David Harris
aff61ea97a
Fixed Linux makefile; load branch predictor RAMs at startup for sim; fixed comment in trap; starting to make testbench more compatible with Verilator
2023-12-13 11:33:59 -08:00
Jacob Pease
7e494f2d3b
Removed vivado property from rom1p1r.sv. It's now dynamically added using the FPGA makefile.
2023-12-01 18:59:18 -06:00
David Harris
8cb433cb66
Commented IROM preloading
2023-11-19 19:33:57 -08:00
Jacob Pease
87e6a5ccf2
Updated ROM to preload bootloader from file and infer a block ram when building for FPGA.
2023-11-18 19:15:39 -06:00
David Harris
7a56a66927
set default USE_SRAM=0 in memories; cleaned up synthesis script grep for cvw_t
2023-11-03 06:37:05 -07:00
David Harris
1f2899de14
Modified rams to take USE_SRAM rather than P to facilitate synthesis
2023-11-03 05:44:13 -07:00
David Harris
31d9ec08cb
Improved comments about memory read paths
2023-11-01 07:00:17 -07:00
David Harris
2d17a991d8
rom1p1r code cleanup
2023-10-30 19:47:49 -07:00
David Harris
3f7c67882f
rom1p1r code cleanup
2023-10-30 19:46:38 -07:00
Ross Thompson
a89a1e675c
Merge branch 'boot' into mergeBoot
...
Merges Jacob's new sdc controller into wally.
2023-07-21 17:43:45 -05:00
Jacob Pease
380d96b359
Working new boot process. Buildroot package for sdc.
2023-07-20 14:15:59 -05:00
Ross Thompson
c82638774f
Updated the FPGA zero stage bootloader.
2023-07-17 15:52:13 -05:00
Ross Thompson
75b5c23edd
Actually removed old `define configuration file for rv64gc. There were a lot of dangling problems.
2023-06-15 14:05:44 -05:00
Ross Thompson
009d8966e9
Got the srams parameterized correctly now.
2023-06-15 13:42:24 -05:00
Ross Thompson
b8a243827b
Found a whole bunch of files still using the old `define configurations.
2023-06-15 13:09:07 -05:00
Jacob Pease
40f81d5da6
The Vivado-RISC-V SDC works. Wally is now booting through it.
2023-05-26 15:42:33 -05:00
Ross Thompson
81074a822a
Merge branch 'main' of https://github.com/openhwgroup/cvw into main
2023-04-09 12:19:44 -05:00
David Harris
7affe2bdca
Waived coverage on BTB memory with byte write enables tied high
2023-04-07 21:56:49 -07:00
Jacob Pease
b796b1b492
Build doesn't work. AXI Crossbar has problems.
2023-04-06 16:01:58 -05:00
Ross Thompson
07b946bc75
Fixed syntax error.
2023-04-06 15:10:55 -05:00
Ross Thompson
4407d3310c
Added note about strange vivado behavior not inferring block ram.
2023-04-06 15:09:35 -05:00
Ross Thompson
ee4cf5e94d
Similifed the no byte write enabled version of the sram model.
2023-04-06 14:18:41 -05:00
Alec Vercruysse
ac3569d75c
Update ram1p1rwe (ce & we) coverage exlusion explanation
2023-04-05 14:54:58 -07:00
Alec Vercruysse
782feb6161
turn off ce coverage for ram1p1rwe
...
According to the textbook, the cache memory chip enable,
`CacheEn`, is only lowered by the cachefsm with it is in the ready
state and a pipeline stall is asserted.
For read only caches, cache writes only occur in the state_write_line
state. So there is no way that a write would happen while the chip
enable is low.
Removing the chip-enable check from this memory to increase coverage
would be a bad idea since if anyone else uses this ram, the behaviour
would be differently than expected. Instead, I opted to turn off
coverage for this statement. Since this ram, which does not have a
byte enable, is used exclusively by read-only caches right now, this
should not mistakenly exclude coverage for other cases, such as D$.
2023-04-05 11:48:18 -07:00
Alec Vercruysse
8b6b96012d
add ram1p1rwe for read-only cache ways (remove byte-enable)
...
- increases coverage
2023-04-05 11:48:18 -07:00
